STM6520

Description

Doc ID 15953 Rev 5

5/23

1

Description

The Smart Reset™ devices provide a useful feature that ensures inadvertent short reset

push-button closures do not cause system resets. This is done by implementing extended

ensures a safe reset and eliminates the need for a specific dedicated reset button.

This reset configuration provides versatility and allows the application to discriminate

between a software generated interrupt and a hard system reset. When the input push-

buttons are connected to microcontroller interrupt inputs, and are closed for a short time, the

processor can only be interrupted. If the system still does not respond properly, continuing

processor through the reset outputs.

The STM6520 has two combined delayed Smart Reset™ inputs (SR0, SR1) with two user-

selected by a dual-state Smart Reset™ DSR input pin. When DSR is connected to ground,

going active simultaneously after both of the Smart Reset™ inputs were held active for the

inactive logic level (for this device the output reset pulse duration is fully push-button

controlled, meaning neither fixed nor minimum reset pulse width, nor power-on reset pulse

is implemented). The first reset output, RST1, is active-low, open-drain; the second reset

1.65 to 5.5 V. Below 1.575 V typ. the inputs are ignored and outputs are deasserted; the

deasserted reset output levels are then valid down to 1.0 V.

Figure 1.

Logic diagram

Figure 2.

Pin connections

AM00434

VCC

RST1

RST2

VSS

STM6520

SR1

SR0

DSR

AM00435

RST1

NC

DSR

1

2

3

STM6520

4

8

7

6

5

RST2

VSS

VCC

SR1

SR0