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PC312XDP512F0CPVR 数据表(PDF) 86 Page - Freescale Semiconductor, Inc

部件名 PC312XDP512F0CPVR
功能描述  HCS12X Microcontrollers
PDF  1348 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

PC312XDP512F0CPVR 数据表(HTML) 86 Page - Freescale Semiconductor, Inc

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Chapter 2 Clocks and Reset Generator (S12CRGV6)
MC9S12XDP512 Data Sheet, Rev. 2.21
86
Freescale Semiconductor
2.3.2.3
Reserved Register (CTFLG)
This register is reserved for factory testing of the CRG module and is not available in normal modes.
Read: Always reads 0x_00 in normal modes
Write: Unimplemented in normal modes
NOTE
Writing to this register when in special mode can alter the CRG
fucntionality.
2.3.2.4
CRG Flags Register (CRGFLG)
This register provides CRG status bits and flags.
Read: Anytime
Write: Refer to each bit for individual write conditions
76543210
R
00000000
W
Reset
00000000
= Unimplemented or Reserved
Figure 2-6. Reserved Register (CTFLG)
76543210
R
RTIF
PORF
LVRF
LOCKIF
LOCK
TRACK
SCMIF
SCM
W
Reset
0
12
00000
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset.
= Unimplemented or Reserved
Figure 2-7. CRG Flags Register (CRGFLG)
Table 2-2. CRGFLG Field Descriptions
Field
Description
7
RTIF
Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
6
PORF
Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power on reset has not occurred.
1 Power on reset has occurred.



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