2-190
RF2157
Rev A19 010611
2
Pin
Function
Description
Interface Schematic
1GND
This pin is internally grounded to the die flag.
2
VPD1
Power down control for first stage. When this pin is “low”, first stage cir-
cuits are shut off. When this pin is 2.8V, all first stage circuits are oper-
ating normally. VPD1 requires a regulated 2.8V for the amplifier to
operate properly over all specified temperature and voltage ranges. A
dropping resistor from a higher regulated voltage may be used to pro-
vide the required 2.8V.
3MODE
For full power operation, VMODE is set low. VMODE will reduce the
bias current by approximately 50% when set HIGH. Large Signal Gain
is reduced approximately 1.5dB at 29dBm POUT. Small Signal Gain is
reduced by approximately 6dB at lower temperatures. An external
series resistor is optional to limit the amount of current required.
4
VPD2
Power down control for the second stage. When this pin is “low”, the
second stage circuit is shut off. When this pin is 2.8V, the second stage
circuit is operating normally. VPD requires a regulated 2.8V for the
amplifier to operate properly over all specified temperature and voltage
ranges. A dropping resistor from a higher regulated voltage may be
used to provide the required 2.8V. A 15pF high frequency bypass
capacitor is recommended.
5GND
Connect to ground plane via 15nH inductor. DC return for the second
stage bias circuit.
6NC
This pin is internally a no connection. It is recommended that this pin
be connected to either the RF output matching network or to the
ground plane.
7RF OUT
RF output and power supply for final stage. This is the unmatched col-
lector output of the second stage. A DC block is required following the
matching components. The biasing may be provided via a parallel L-C
set for resonance at the operating frequency of 1710MHz to 1910MHz.
It is important to select an inductor with very low DC resistance with a
1A current rating. Alternatively, shunt microstrip techniques are also
applicable and provide very low DC resistance. Low frequency bypass-
ing is required for stability.
8RF OUT
Same as pin 7.
See pin 7.
9GND
This pin is internally grounded to the die flag.
10
VCC
Supply for bias reference and control circuits. High frequency bypass-
ing may be necessary.
11
VCC1
Power supply for first stage and interstage match. Pins 11 and 12
should be connected by a common trace where the pins contact the
printed circuit board.
12
VCC1
Same as pin 11.
13
NC
This pin is internally a no connection. It is recommended that this pin
be connected to either VCC1 or to the ground plane.
14
NC
It is recommended that these pins be connected to the ground plane for
improved isolation between RF IN (pin 16) and the VCC1 pins (pins 11
and 12).
15
NC
It is recommended that these pins be connected to the ground plane for
improved isolation between RF IN (pin 16) and the VCC1 pins (pins 11
and 12).
16
RF IN
RF input. An external 15pF series capacitor is required as a DC block.
In addition, a series transmission line and shunt capacitor, 5pF, are
required to provide 2:1 VSWR.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias. The pad should have a short thermal path to the ground
plane.
RF OUT
From Bias
Network
GND1
RF IN
VCC1
From
Bias
Stages
15 pF
5pF
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