
Preliminary
2-207
RF2192
Rev A1 010830
2
Pin
Function
Description
Interface Schematic
1GND
Ground connection.
2GND
Ground connection.
3GND
Ground connection.
4RF IN
RF input. An external 100pF series capacitor is required as a DC block.
In addition, shunt inductor and series capacitor are required to provide
2:1VSWR.
5VREG1
Power Down control for first stage. Regulated voltage supply for ampli-
fier bias. In Power Down mode, both VREG and VMODE need to be LOW
(<0.5V).
6VMODE
For nominal operation (High Power Mode), VMODE is setLOW.When
set HIGH, the driver and final stage are dynamically scaled to reduce
the device size and as a result to reduce the idle current.
7VREG2
Power Down control for the second stage. Regulated voltage supply for
amplifier bias. In Power Down mode, both VREG and VMODE need to be
LOW (< 0.5V).
8BIAS GND
Bias circuitry ground. See application schematic.
9GND
Ground connection.
10
RF OUT
RF output and power supply for final stage. This is the unmatched col-
lector output of the second stage. A DC block is required following the
matching components. The biasing may be provided via a parallel L-C
set for resonance at the operating frequency of 824MHz to 849MHz. It
is important to select an inductor with very low DC resistance with a 1A
current rating. Alternatively, shunt microstrip techniques are also appli-
cable and provide very low DC resistance. Low frequency bypassing is
required for stability.
11
RF OUT
Same as pin 10.
See pin 10.
12
RF OUT
Same as pin 10.
13
2FO
Harmonic trap. This pin connects to the RF output but is used for pro-
viding a low impedance to the second harmonic of the operating fre-
quency. An inductor or transmission line resonating with an on chip
capacitor at 2fo is required at this pin.
14
VCC BIAS
Power supply for bias circuitry. A 100pF high frequency bypass capaci-
tor is recommended.
15
VCC1
Power supply for first stage.
16
VCC1
Same as Pin 15.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias. The pad should have a short thermal path to the ground
plane.
GND1
RF IN
VCC1
From
Bias
Stages
100 pF
RF OUT
From Bias
Stages