SC415_08 datasheet(17/30 Pages) SEMTECH

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SC415

With a peak voltage V

PEAK

of 1.98V (180mV or 10% rise

above 1.8V upon load release), the required capacitance

is,

COUT

MIN

= 1.5μH × (10 + 1/2 • 4.2)2 / (1.982 - 1.82)

COUT

MIN

= 323μF

The above requirements (323μF, 6.4mΩ) can be met using

a single 330μF 6mΩ capacitor.

Note that output voltage ripple is often higher than

expected due to the ESL (inductance) of the capacitor.

See the Stability Considerations section.

If the load release is relatively slow, the output capacitance

can be reduced. At heavy loads during normal switching,

when the FB pin is above the 750mV reference, the DL

output is high and the low-side MOSFET is on. During

this time, the voltage across the inductor is approximately

-VOUT. This causes a down-slope or falling di/dt in the

inductor. If the load di/dt is not much faster than the di/dt

in the inductor, then the inductor current can track change

in load current, and there will be relatively less overshoot

from a load release. The following formula can be used to

calculate the needed capacitance for a given dILOAD/dt.

PEAK

= IMAX + 1/2 × I

RIPPLEMAX

PEAK

= 10 + 1/2 × 4.2 = 12.1A

Rate of change of Load current = dILOAD/dt

IMAX = maximum DC load current

= 10A

OUT

= IL

PEAK

× (L ×IL

PEAK

/ V

OUT

- I

MAX

/dILOAD /dt)

_________________________________

2 × (V

PEAK

- V

OUT

)

Example: Load dI/dt = 2.5A/μsec

This would cause the output current to move from 10A

to zero in 4μsec.

OUT

= 12.1× (1.5μH×12.1/1.8 - 10/(2.5/1μsec)

________________________________

2 × (1.98 - 1.8)

OUT

= 204 μF

Applications Information (continued)

Note that 204μF is less than the 330μF needed to meet

the harder (instantaneous) transient load release.

Stability Considerations

Unstable operation shows up in two related but distinctly

different ways: fast-feedback loop instability due to

insufficient ESR and double-pulsing.

Loop instability can cause oscillations at the output as

a response to line or load transients. These oscillations

can trip the over-voltage protection latch or cause the

output voltage to fall below the tolerance limit. The best

way for checking stability is to apply a zero-to-full load

transient and observe the output voltage ripple envelope

for overshoot and ringing. Over one cycle of ringing after

the initial step is a sign that the ESR should be increased.

SC415 ESR Requirements

The on-time control used in the SC415 regulates the

valley of the output ripple voltage. This ripple voltage

consists of a term generated by the ESR of the output

capacitor and a term based on the capacitance charging

and discharging during the switching cycle. A minimum

ESR is required to generate the required ripple voltage for

regulation. For most applications the minimum ESR ripple

voltage is dominated by PCB layout and the properties of

the output capacitors, typically SP or POSCAP devices.

For stability the ESR zero of the output capacitor should

be lower than one-third the switching frequency. The

formula for minimum ESR is:

ESRMIN = 3 / (2 × π × COUT × FREQ)

For applications using ceramic output capacitors, the ESR

is generally too small to meet the above criteria. In these

cases it is possible to create a ripple voltage ramp that

mimics the ESR ramp.

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