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SSTUB32864EC/G 数据表(PDF) 13 Page - NXP Semiconductors |
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SSTUB32864EC/G 数据表(HTML) 13 Page - NXP Semiconductors |
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13 / 19 page ![]() SSTUB32864_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 26 March 2007 13 of 19 NXP Semiconductors SSTUB32864 1.8 V configurable registered buffer for DDR2-800 RDIMM applications 11.2 Output slew rate measurement VDD = 1.8 V ± 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z 0 =50 Ω; input slew rate=1V/ns ± 20 %, unless otherwise specified. (1) CL includes probe and jig capacitance. Fig 12. Load circuit, HIGH-to-LOW slew measurement Fig 13. Voltage waveforms, HIGH-to-LOW slew rate measurement (1) CL includes probe and jig capacitance. Fig 14. Load circuit, LOW-to-HIGH slew measurement Fig 15. Voltage waveforms, LOW-to-HIGH slew rate measurement CL = 10 pF(1) VDD OUT DUT test point RL = 50 Ω 002aaa377 VOH VOL output 80 % 20 % dv_f dt_f 002aaa378 CL = 10 pF(1) OUT DUT test point RL = 50 Ω 002aaa379 VOH VOL 80 % 20 % dv_r dt_r output 002aaa380 |
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