4 / 14 page
Preliminary
3-30
RF3322
Rev A2 010518
3
Serial Bus Block Diagram
Pin
Function
Description
Interface Schematic
1GND
Connect to ground.
2
VCC1
This pin is connected to the supply voltage, and should be decoupled
as close to GND1 as possible.
3GND
Connect to ground.
4
GND1
PGA RF ground.
5V IN+
Input pin. This should be externally AC-coupled to signal source.
6V IN-
Complementary input pin. This should be externally coupled to signal
source. For single-ended use, this pin should be AC-coupled to ground
through an impedance equivalent to the impedance driving V IN+.
7GND
Connect to ground.
8CS
Serial bus enable.
9SDA
Serial bus data input.
10
SCLK
Serial bus clock input.
11
GND
Connect to ground.
12
SHDN
Ship shutdown pin. Forcing a logic low causes all circuits to switch off
andgainsettingstobelost.
13
NC
Not connected.
14
RAMP
Turn-on time is controlled by an external capacitor between this pin and
ground.
15
V OUT-
Open collector output. Connect to VCC via balun primary.
16
V OUT+
Open collector output. Connect to VCC via balun primary.
17
NC
Not connected.
18
TXEN
Signal path enable pin. Logic high turns on signal path. Logic low turns
off signal path, but leaves serial bus active.
19
VCC2
This pin is connected to the supply voltage, and should be decoupled
as close to GND2 as possible.
20
GND2
Power amplifier bias ground.
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D0
D1
D2
D3
D4
D5
D6
POR
CS
SDA
SCLK
D
CK
Q
CLR
D
CK
Q
CLR
D7
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
