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Preliminary
3-31
RF3322
Rev A2 010518
3
Table 1. Serial Interface Control Word Format
Serial Bus Timing Diagram
Table 2. Timing Data
Table 3. Programming State
Bit
Mnemonic
Description
MSB 7
D7
Sleep Mode (Software Shutdown)
6D6
Test Bit
5
D5
Gain Control, Bit 5
4
D4
Gain Control, Bit 4
3
D3
Gain Control, Bit 3
2
D2
Gain Control, Bit 2
1
D1
Gain Control, Bit 1
LSB 0
D0
Gain Control, Bit LSB
Parameter
Symbol
Min
Typ
Max
Units
SCLK Pulsewidth
TWH
50
ns
SCLK Period
TC
100
ns
Setup Time, SDA versus S CLK
TDS
10
ns
Setup Time, CS versus S CLK
TES
10
ns
Hold Time, SDA versus S CLK
TDH
20
ns
Hold Time, CS versus S CLK
TEH
20
ns
SCLK Pulsewidth, High
TDATAH
50
ns
SCLK Pulsewidth, Low
TDATAL
50
ns
TX
SHDND
MSB6
Enter Sleep Mode
X
H
L
H= High Voltage Logic
Exit Sleep Mode
X
H
H*
L=Low Voltage Logic
Enter Shutdown
X
L
X
X =Don’t Care
Exit Shutdown
X
H
H*
*Gain Control Data Must be Re-Sent
TX Enable
H
X
X
TX Disable
L
X
X
D0
D1
D2
D3
D4
D5
D6
TES
TDS
TDH
TEH
TWH
TC
TDATAH,TDATAL
D7
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