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SA9401 数据表(PDF) 3 Page - Sames |
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SA9401 数据表(HTML) 3 Page - Sames |
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3 / 16 page ![]() sames SA9401 3 37, 36, 35, 33, I D0..D7 EPROM Data Lines 32, 31, 30, 29 9, 14, 19 I PS0, PS1, Program Select Inputs for Selecting PS2 between 1 of 8 tone plans 7 O CLKDIV2 CLKIN divided by 2 output (i.e. 4096 kHz or 1024 kHz depending on CLK_SEL input) 40 I CLK_SEL Selects between CKLIN of 8192 or 2048 kHz and Synchronisation source. 0 = 8192kHz/Internal 1 = 2048kHz/External 28 I TEST Used for IC testing purpose. Tied Low during normal operation. 38 I MRST Asynchronous Reset Pin. Resets all Internal Flip Flops (active low) 16 I WD_RST Watchdog reset input (Rising-edge triggered) Tied high if unused 17 I WD_EN Watchdog enable input (active low) Tied high if unused 18 O WD_INT Watchdog output (active low, tri-state) PIN DESCRIPTION (Continued) Pin No I/0 Designation Description BLOCK DIAGRAM CLOCK GENERATOR PCM_OU A[13 : 0] INTRCAD 8KFS INTRFRQ WD_INT PCMFSC 2MCLK CLKDIV2 SA9401 DR-01085 T EST P S[2 : 0] / FS1 D [7 : 0] WDENB WD_RST C LKIN / MRST C LK_SEL WATCHDOG TIMER CADENCE TIMER PCM INTERFACE EPROM INTERFACE INTRUDE TONE GENERATOR |
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