KM416RD8AS-RBM80 datasheet(13/64 Pages) SAMSUNG

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KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

DQ Packet Timing

Figure 4 shows the timing relationship of COLC packets

with D and Q data packets. This document uses a specific

convention for measuring time intervals between packets: all

packets on the ROW and COL pins (ROWA, ROWR,

COLC, COLM, COLX) use the trailing edge of the packet as

a reference point, and all packets on the DQA/DQB pins (D

and Q) use the leading edge of the packet as a reference

point.

An RD or RDA command will transmit a dualoct of read

data Q a time tCAC later. This time includes one to five

cycles of round-trip propagation delay on the Channel. The

tCAC parameter may be programmed to a one of a range of

values ( 8, 9, 10, 11, or 12 tCYCLE). The value chosen

depends upon the number of RDRAM devices on the

Channel and the RDRAM timing bin. See Figure 39 for

more information.

A WR or WRA command will receive a dualoct of write

data D a time tCWD later. This time does not need to include

the round-trip propagation time of the Channel since the

COLC and D packets are traveling in the same direction.

When a Q packet follows a D packet (shown in the left half

of the figure), a gap (tCAC -tCWD) will automatically appear

between them because the tCWD value is always less than the

tCAC value. There will be no gap between the two COLC

packets with the WR and RD commands which schedule the

D and Q packets.

When a D packet follows a Q packet (shown in the right half

of the figure), no gap is needed between them because the

tCWD value is less than the tCAC value. However, , a gap of

tCAC -tCWD or greater must be inserted between the COLC

packets with the RD WR commands by the controller so the

Q and D packets do not overlap.

COLM Packet to D Packet Mapping

Figure 5 shows a write operation initiated by a WR

command in a COLC packet. If a subset of the 16 bytes of

write data are to be written, then a COLM packet is trans-

mitted on the COL pins a time tRTR after the COLC packet

containing the WR command. The M bit of the COLM

packet is set to indicate that it contains the MA and MB

mask fields. Note that this COLM packet is aligned with the

COLC packet which causes the write buffer to be retired.

See Figure 17 for more details.

If all 16 bytes of the D data packet are to be written, then no

further control information is required. The packet slot that

would have been used by the COLM packet (tRTR after the

COLC packet) is available to be used as an COLX packet.

This could be used for a PREX precharge command or for a

housekeeping command (this case is not shown). The M bit

is not asserted in an COLX packet and causes all 16 bytes of

the previous WR to be written unconditionally. Note that a

RD command will never need a COLM packet, and will

always be able to use the COLX packet option (a read opera-

tion has no need for the byte-write-enable control bits).

Figure 5 also shows the mapping between the MA and MB

fields of the COLM packet and bytes of the D packet on the

DQA and DQB pins. Each mask bit controls whether a byte

of data is written (=1) or not written (=0).

Figure 4: Read (Q) and Write (D) Data Packet - Timing for tCAC = 8, 9, 10, 11, or 12 tCYCLE

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T24

T28

T17

T21

T25

T29

T18

T22

T26

T30

T19

T23

T27

T31 T32

T36

T40

T44

T33

T37

T41

T45

T34

T38

T42

T46

T35

T39

T43

T47

RD b1

Q (a1)

WR a1

D (a1)

tCWD

RD c1

Q (a1)

tCAC -tCWD

This gap on the DQA/DQB pins appears automatically

This gap on the COL pins must be inserted by the controller

tCAC

WR d1

D (d1)

tCAC-tCWD

tCWD

WR d1

Q (c1)

• • •

WR d1

• • •

D (d1)

Q (c1)

D (d1)

Q (c1)

• • •

Q (a1)

Q (b1)

WR d1

D (d1)

Q (c1)

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