YZT PACKAGE

(TOP VIEW)

D

C

B

A

3 2 1

TXB0104

SCES650E – APRIL 2006 – REVISED FEBRUARY 2010

www.ti.com

TERMINAL ASSIGNMENTS

(YZT Package)

3

2

1

D

A4

GND

B4

C

A3

OE

B3

B

A2

B2

A

A1

B1

DESCRIPTION/ORDERING INFORMATION

This 4-bit noninverting translator uses two separate configurable power-supply rails. The A port is designed to

accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state. To ensure the

high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor;

the minimum value of the resistor is determined by the current-sourcing capability of the driver.

preventing damaging current backflow through the device when it is powered down.

ORDERABLE PART NUMBER

NanoFree™ — WCSP (DSBGA)

0.23-mm Large Bump – YZT

Reel of 3000

TXB0104YZTR

_ _ _ 2 K _

(Pb-free) 0.625-mm max height

UFBGA – GXU

Reel of 2500

TXB0104GXUR

YE04

UFBGA – ZXU (Pb-Free)

Reel of 2500

TXB0104ZXUR

YE04

TXB0104RGYR

QFN – RGY

Reel of 1000

YE04

TXB0104RGYRG4

–40°C to 85°C

uQFN – RUT

Reel of 1000

TXB0104RUTR

2KR

TXB0104D

Tube of 50

TXB0104DG4

SOIC – D

TXB0104

TXB0104DR

Reel of 2500

TXB0104DRG4

TXB0104PWR

TSSOP – PW

Reel of 2000

YE04

TXB0104PWRG4

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3)

YZT: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

2

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Product Folder Link(s): TXB0104