AD9550

Rev. 0 | Page 3 of 20

SPECIFICATIONS

Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY VOLTAGE

3.135

3.30

3.465

V

Pin 18, Pin 21, and Pin 28

POWER CONSUMPTION

Tested with both output channels active at maximum

output frequency; LVPECL and LVDS outputs use a 100 Ω

termination between both pins of the output driver

Total Current

162

185

mA

VDD Current By Pin

Pin 18

93

106

mA

Pin 21

LVDS Configured Output

35

41

mA

LVPECL Configured Output

36

42

mA

CMOS Configured Output

29

34

mA

Pin 28

LVDS Configured Output

35

41

mA

LVPECL Configured Output

36

42

mA

CMOS Configured Output

29

34

mA

LOGIC INPUT PINS

Input Characteristics1

Logic 1 Voltage, V

IH

1.02

V

For the CMOS inputs, a static Logic 1 results from either

a pull-up resistor or no connection

Logic 0 Voltage, V

IL

0.64

V

Logic 1 Current, I

IH

3

µA

Logic 0 Current, I

IL

17

µA

LOGIC OUTPUT PINS

Output Characteristics

Tested at 1 mA load current

Output Voltage High, V

OH

2.7

V

Output Voltage Low, V

OL

0.19

V

RESET Pin

Input Characteristics2

Input Voltage High, V

IH

1.96

V

Input Voltage Low, V

IL

0.85

V

Input Current High, I

INH

0.3

12.5

µA

Input Current Low, I

INL

31

43

µA

Minimum Pulse Width Low

150

µs

Tested with an active source driving the RESET pin

REFERENCE CLOCK INPUT CHARACTERISTICS

CMOS Single-Ended Input

Input Frequency Range

0.008

200

MHz

Input High Voltage

1.62

V

Input Low Voltage

0.52

V

Input Threshold Voltage

1.0

V

When ac coupling to the input receiver, the user must

dc bias the input to 1 V

Input High Current

0.04

µA

Input Low Current

0.03

µA

Input Capacitance

3

pF

Duty Cycle

Pulse width high and pulse width low establish the

bounds for duty cycle

Pulse Width Low

2

ns

Pulse Width High

2

ns