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ADP2302ARDZ-3.3-R7 数据表(PDF) 16 Page - Analog Devices |
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ADP2302ARDZ-3.3-R7 数据表(HTML) 16 Page - Analog Devices |
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16 / 28 page ![]() ADP2302/ADP2303 Rev. 0 | Page 16 of 28 APPLICATIONS INFORMATION PROGRAMMING OUTPUT VOLTAGE ADP2302/ADP2303 have an adjustable version where the output voltage is programmed through an external resistive divider, as shown in Figure 45. Suggested resistor values for the typical output voltage setting are listed in Table 6. The output voltages are calculated using the following equation: ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + × = BOT TOP OUT R R V 1 V 800 . 0 where: VOUT is the output voltage. RTOP is the feedback resistor from VOUT to FB. RBOT is the feedback resistor from FB to GND. VOUT RTOP RBOT ADP2302/ ADP2303 FB Figure 45. Programming the Output Voltage Using a Resistive Voltage Divider Table 6. Suggested Values for Resistive Voltage Divider VOUT (V) RTOP (kΩ), ±1% RBOT (kΩ), ±1% 1.2 10 20 1.5 10 11.3 1.8 12.7 10.2 2.5 21.5 10.2 3.3 31.6 10.2 5.0 52.3 10 VOLTAGE CONVERSION LIMITATIONS There are both lower and upper output voltage limitations for a given input voltage due to the minimum on time, the minimum off time, and the bootstrap dropout voltage. The lower limit of the output voltage is constrained by the controllable minimum on time, which can be as high as 170 ns for the worst case. By considering the variation of both the switch- ing frequency and the input voltage, the equation for the lower limit of the output voltage is VOUT(min) = tMIN-ON × fSW(max) × (VIN(max) + VD) − VD where: VIN(max) is the maximum input voltage. fSW(max) is the maximum switching frequency for the worst case. tMIN-ON is the minimum controllable on time. VD is the diode forward drop. The upper limit of the output voltage is constrained by the mini- mum controllable off time, which can be as high as 280 ns in ADP2302/ADP2303 for the worst case. By considering the variation of both the switching frequency and the input voltage, the equation for the upper limit of the output voltage is VOUT(max) = tMIN-OFF × fSW(max) × (VIN(min) + VD) − VD where: VIN(min) is the minimum input voltage. fSW(max) is the maximum switching frequency for the worst case. VD is the diode forward drop. tMIN-OFF is the minimum controllable off time. In addition, the bootstrap circuit limits the minimum input voltage for the desired output due to the internal dropout voltage. To attain stable operation at light loads and ensure proper startup for the prebiased condition, the ADP2302/ADP2303 require the voltage difference between the input voltage and the regulated output voltage (or between the input voltage and the prebias voltage) to be greater than 2.1 V for the worst case. If the voltage difference is smaller, the bootstrap circuit relies on some minimum load current to charge the boost capacitor for startup. Figure 46 shows the typical required minimum input voltage vs. load current for the 3.3 V output voltage. 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 1 10 100 1000 OUPTUT CURRENT (mA) FOR START UP WHILE IN OPERATION Figure 46. Minimum Input Voltage vs. Load Current Based on three conversion limitations (the minimum on time, the minimum off time, and the bootstrap dropout voltage), Figure 47 shows the voltage conversion limitations. |
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