_______________________________________________________________________________________ 3

20-Bit, Single-Channel, Ultra-Low-Power, Delta-

Sigma ADCs with Programmable Gain and GPIO

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Absolute Input Voltage

Low input voltage

Buffers disabled

30mV

V

Buffers enabled

100mV

High input voltage

Buffers disabled

30mV

Buffers enabled

100mV

DC Input Leakage

Sleep mode

Q

1

F

A

AIN Dynamic Input Current

Buffer disabled

Q

1.4

F

A/V

Buffer enabled

Q

20

nA

REF Dynamic Input Current

Buffer disabled

Q

2.1

F

A/V

Buffer enabled

Q

30

nA

AIN Input Capacitance

Buffer disabled

5

pF

REF Input Capacitance

Buffer disabled

7.5

pF

AIN Voltage Range

Unipolar

0

V

Bipolar

Input Sampling Rate

LINEF = 0

246

kHz

LINEF = 1

204.8

REF Voltage Range

Buffers disabled

0

V

Buffers enabled

0.1

- 0.1

REF Sampling Rate

LINEF = 0

246

kHz

LINEF = 1

204.8

LOGIC INPUTS (SCLK, CLK, DIN, GPIO1–GPIO4)

Input Current

Input leakage current

Q

1

F

A

Input Low Voltage

0.3 x

V

Input High Voltage

0.7 x

V

Input Hysteresis

200

mV

External Clock

60Hz line frequency

2.4576

MHz

55Hz line frequency

2.25275

50Hz line frequency

2.048

LOGIC OUTPUTS (RDY/DOUT, GPIO1–GPIO4)

Output Low Level

0.4

V

Output High Level

0.9 x

V

Leakage Current

High-impedance state

Q

500

nA

Output Capacitance

High-impedance state

9

pF