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MAX11206 数据表(PDF) 4 Page - Maxim Integrated Products |
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MAX11206 数据表(HTML) 4 Page - Maxim Integrated Products |
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4 / 27 page ![]() 4 ______________________________________________________________________________________ 20-Bit, Single-Channel, Ultra-Low-Power, Delta- Sigma ADCs with Programmable Gain and GPIO ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, single-cycle mode (SCYCLE = 1), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization. Note 3: VAINP = VAINN. Note 4: ppmFSR is parts per million of full scale. Note 5: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. Note 6: For data rates (1, 2.5, 5, 10, 15)sps and (0.83, 2.08, 4.17, 8.33, 12.5)sps. Note 7: Normal-mode rejection of power line frequencies of 60Hz/50Hz apply only for single-cycle data rates at 15sps/10sps and lower or continuous data rate of 60sps/50sps. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Analog Supply VAVDD 2.7 3.6 V Digital Supply VDVDD 1.7 3.6 V Total Operating Current AVDD + DVDD Buffers disabled 235 300 F A Buffers enabled 255 AVDD Sleep Current 0.15 2 F A AVDD Operating Current Buffers disabled 185 235 F A Buffers enabled 205 DVDD Sleep Current 0.25 2 F A DVDD Operating Current 50 65 F A SPI TIMING CHARACTERISTICS SCLK Frequency fSCLK 5 MHz SCLK Clock Period tCP 200 ns SCLK Pulse-Width High tCH 80 ns SCLK Pulse-Width Low tCL 60% duty cycle at 5MHz 80 ns CS Low to 1st SCLK Rise Setup tCSS0 40 ns CS High to 17th SCLK Setup tCSS1 40 ns CS High After 16th SCLK Falling Edge Hold tCSH1 3 ns CS Pulse-Width High tCSW 40 ns DIN to SCLK Setup tDS 40 ns DIN Hold After SCLK tDH 0 ns RDY/DOUT Transition Valid After SCLK Fall tDOT Output transition time, data changes on fall- ing edge of SCLK 40 ns RDY/DOUT Remains Valid After SCLK Fall tDOH Output hold time allows for negative edge data read 3 ns RDY/DOUT Valid Before SCLK Rise tDOL tDOL = tCL - tDOT 40 ns CS Rise to RDY/DOUT Disable tDOD CLOAD = 20pF 25 ns CS Fall to RDY/DOUT Valid tDOE Default value of RDY is 1 for minimum spec- ification; maximum specification for valid 0 on RDY/DOUT 0 40 ns DATA Fetch tDF Maximum time after RDY asserts to read DATA register; tCNV is the time for one conversion 0 tCNV - 60 x tCP |
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