WM8711SEDSSLASHR datasheet(24/47 Pages) WOLFSON

24 / 47 page

Production Data

WM8711 / WM8711L

PD Rev 4.4 April 2007

CLOCKOUT

The Core Clock is internally buffered and made available externally to the audio system on the

CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for

driving external loads.

There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will

inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to

Electrical Characteristics.

CLKOUT can also be divided by 2 under software control, refer to Table 8. Note that if CLKOUT is not

required then the CLKOUT buffer on the WM8711/L can be safely powered down to conserve power

(see POWER DOWN section). If the system architect has the choice between using FCLKOUT = FMCLK

or FCLKOUT = FMCLK/2 in the interface, the latter is recommended to conserve power. When the divide

by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical

Characteristics for timing information.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001000

Sampling

Control

CLKODIV2

CLKOUT divider select

1 = CLOCKOUT is Core Clock divides

by 2

0 = CLOCKOUT is Core Clock

Table 8 Programming CLKOUT

CLKOUT is disabled and set low whenever the device is in reset.

DIGITAL AUDIO INTERFACES

WM8711/L may be operated in either one of the 4 offered audio interface modes. These are:

•

Right justified

•

Left justified

•

DSP mode

All four of these modes are MSB first and operate with data 16 to 32 bits, except in right justified

mode where 32 bit data is not supported.

The digital audio interface receives the digital audio data for the internal DAC digital filters on the

DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters

with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether

Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous with the

BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always an input.

BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave

mode. Refer to the MASTER/SLAVE OPERATION section

WM8711SEDS/R 数据表(PDF) 24 Page - Wolfson Microelectronics plc

WM8711SEDS/R 数据表(HTML) 24 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

数据表下载