ATSAM3S datasheet(33/65 Pages) ATMEL

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6500AS–ATARM–11-Dec-09

SAM3S Summary

9.1.3.9

Fast Flash Programming Interface

The Fast Flash Programming Interface allows programming the device through either a serial

JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program-

ming with market-standard industrial programmers.

The FFPI supports read, page program, page erase, full erase, lock, unlock and protect

commands.

The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered

when TST and PA0 and PA1are tied low.

9.1.3.10

SAM-BA

® Boot

The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the

on-chip Flash memory.

The SAM-BA Boot Assistant supports serial communication via the UART and USB.

The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).

The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.

9.1.3.11

GPNVM Bits

The SAM3S features three GPNVM bits that can be cleared or set respectively through the com-

mands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.

9.1.4

Boot Strategies

The system always boots at address 0x0. To ensure maximum boot possibilities, the memory

layout can be changed via GPNVM.

A general-purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the

Flash.

The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-

pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.

Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM.

Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default.

9.2

External Memories

The SAM3S features an External Bus Interface to provide the interface to a wide range of exter-

nal memories and to any parallel peripheral.

9.2.1

Static Memory Controller

•8-bit Data Bus

• Up to 24-bit Address Bus (up to 16 MBytes linear per chip select)

• Up to 4 chip selects, Configurable Assignment

• Multiple Access Modes supported

Table 9-2.

General Purpose Non-volatile Memory Bits

GPNVMBit[#]

Function

Security bit

Boot mode selection

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