13

FN6666.4

December 22, 2008

The PGOOD pin indicates when the converter is capable of

supplying regulated voltage. It is an undefined impedance if

falling threshold. When a fault is detected, the ISL62391,

ISL62392 will turn on the open-drain NMOS, which will pull

PGOOD low with a nominal impedance of 32

Ω. This will flag

the system that one of the output voltages is out of regulation.

Separate enable pins allow for full soft-start sequencing.

Because low shutdown quiescent current is necessary to

prolong battery life in notebook applications, the PVCC 5V

LDO is held off until any of the three enable signals (EN1,

EN2 or LDO3EN) are pulled high. Soft-start of all outputs will

only start until after PVCC is above the 4.2V POR threshold.

In addition to user-programmable sequencing, the ISL62391,

ISL62392 includes a pre-programmed sequential SMPS

soft-start feature. Table 1 shows the SMPS enable truth table.

MOSFET Gate-Drive Outputs LGATE and UGATE

The ISL62391, ISL62392 has internal gate-drivers for the

high-side and low-side N-Channel MOSFETs. The low-side

gate-drivers are optimized for low duty-cycle applications

where the low-side MOSFET conduction losses are

pull-down resistance is small in order to clamp the gate of

transient through the gate at turn-off can be considerable

large. Adaptive shoot-through protection prevents a gate-driver

output from turning on until the opposite gate-driver output has

fallen below approximately 1V. The dead-time shown in Figure

25 is extended by the additional period that the falling gate

voltage stays above the 1V threshold. The typical dead-time is

21ns. The high-side gate-driver output voltage is measured

across the UGATE and PHASE pins while the low-side gate-

driver output voltage is measured across the LGATE and

PGND pins. The power for the LGATE gate-driver is sourced

directly from the PVCC pin. The power for the UGATE gate-

driver is sourced from a “boot” capacitor connected across the

BOOT and PHASE pins. The boot capacitor is charged from

the 5V PVCC supply through a “boot diode” each time the low-

side MOSFET turns on, pulling the PHASE pin low. The

ISL62391, ISL62392 has integrated boot diodes connected

from the PVCC pins to BOOT pins.

Diode Emulation

FCCM is a logic input that controls the power state of the

ISL62391, ISL62392. If forced high, the ISL62391, ISL62392

will operate in forced continuous-conduction-mode (CCM)

over the entire load range. This will produce the best transient

response to all load conditions, but will have increased

light-load power loss. If FCCM is forced low, the ISL62391,

ISL62392 will automatically operate in Diode Emulation Mode

(DEM) at light load to optimize efficiency in the entire load

range. The transition is automatically achieved by detecting

the load current and turning off LGATE when the inductor

current reaches 0A.

Positive-going inductor current flows from either the source

of the high-side MOSFET, or the drain of the low-side

MOSFET. Negative-going inductor current flows into the

drain of the low-side MOSFET. When the low-side MOSFET

conducts positive inductor current, the phase voltage will be

negative with respect to the GND and PGND pins.

Conversely, when the low-side MOSFET conducts negative

inductor current, the phase voltage will be positive with

respect to the GND and PGND pins. The ISL62391,

TABLE 1. SMPS ENABLE SEQUENCE LOGIC

EN1

EN2

START-UP SEQUENCE

0

0

All SMPS outputs OFF

0

FLOAT

All SMPS outputs OFF

0

1

SMPS1 OFF, SMPS2 ON

FLOAT

0

All SMPS outputs OFF

FLOAT

FLOAT

All SMPS outputs OFF

FLOAT

1

SMPS1 enables after SMPS2 is in regulation

1

0

SMPS1 ON, SMPS2 OFF

1

FLOAT

SMPS2 enables after SMPS1 is in regulation

1

1

All SMPS outputs ON simultaneously

FIGURE 24. SOFT-START SEQUENCE FOR ONE SMPS

VCC AND PVCC

VO

EN

PGOOD

FB

1.5ms

2.75ms

PGOOD DELAY

FIGURE 25. LGATE AND UGATE DEAD-TIME

50%

50%

UGATE

LGATE

ISL62391, ISL62392