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FN6666.4

December 22, 2008

compensation components close to the VOUT, FB, and GND

pins, keeping the high impedance trace short.

FSET (Pins 2 and 6)

this pin. Keep fast moving nodes away from this pin.

LGATE (Pins 15 and 20)

The signal going through this trace is both high dv/dt and

high di/dt, with high peak charging and discharging current.

Route this trace in parallel with the trace from the PGND pin.

These two traces should be short, wide, and away from

other traces. There should be no other weak signal traces in

proximity with these traces on any layer.

BOOT (Pins 14 and 21), UGATE (Pins 13 and 22), and

PHASE (Pins 12 and 23)

The signals going through these traces are both high dv/dt

and high di/dt, with high peak charging and discharging

current. Route the UGATE and PHASE pins in parallel with

short and wide traces. There should be no other weak signal

traces in proximity with these traces on any layer.

Copper Size for the Phase Node

The parasitic capacitance and parasitic inductance of the

phase node should be kept very low to minimize ringing. It is

best to limit the size of the PHASE node copper in strict

accordance with the current and thermal management of the

application. An MLCC should be connected directly across

the drain of the upper MOSFET and the source of the lower

MOSFET to suppress the turn-off voltage spike.

ISL62391, ISL62392