DS3151N datasheet(13/61 Pages) MAXIM

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

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Table 4-D. Global Pin Descriptions

NAME

I/O

FUNCTION

HIZ

IPU

High-Z Enable Input (Active Low, Open Drain)

0 = tri-state all output pins (Note that the

JTRST pin must be low.)

1 = normal operation

RST

IPU

Reset Input (Active Low, Open Drain, Internal 10k

Ω Pullup to V

DD). When this global asynchronous

reset is pulled low, the internal circuitry is reset and the internal registers (CPU bus mode) are forced

to their default values. The device is held in reset as long as

RST is low. RST should be held low for

at least two master clock cycles.

Hardwired Mode Select

0 = CPU bus mode

1 = hardwired mode

See Section 3 for details.

T3MCLK

T3 Master Clock. A transmission-quality DS3 (44.736MHz

±20ppm, low jitter) clock should be applied

at this pin. Wiring T3MCLK high forces LIUs in DS3 mode to use TCLK for receiver clock and data

recovery.

E3MCLK

E3 Master Clock. A transmission-quality E3 (34.368MHz

±20ppm, low jitter) clock should be applied

at this pin. Wiring E3MCLK high forces LIUs in E3 mode to use TCLK for receiver clock and data

recovery.

STMCLK

STS-1 Master Clock. A transmission-quality STS-1 (51.840MHz

±20ppm, low jitter) clock should be

applied at this pin. Wiring STMCLK high forces LIUs in STS-1 mode to use TCLK for receiver clock

and data recovery.

PRBSn

PRBS Detector Output. This signal reports the status of the PRBS detector. See Section 8 for further

details.

LLBn,

RLBn

Local Loopback Select, Remote Loopback Select

{LLB, RLB} =

00 = no loopback

01 = remote loopback

10 = analog local loopback

11 = digital local loopback

E3Mn

E3 Mode Enable

0 = DS3 operation

1 = E3 or STS-1 operation

STSn

STS-1 Mode Enable

When E3M = 1,

0 = E3 operation

1 = STS-1 operation

When E3M = 0, STS selects the DS3 AIS pattern.

RBIN

Receiver Binary Framer-Interface Enable

0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is

disabled.

1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code

violations. The B3ZS/HDB3 encoder is enabled.

TBIN

Transmitter Binary Framer-Interface Enable

0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder is

disabled.

1 = Transmitter framer interface is binary on the TDAT pin. (TNEG is ignored and should be wired

low.) The B3ZS/HDB3 encoder is enabled.

RCINV

Receiver Clock Invert

0 = RPOS/RDAT and RNEG/RLCV update on the falling edge of RCLK.

1 = RPOS/RDAT and RNEG/RLCV update on the rising edge of RCLK.

TCINV

Transmitter Clock Invert

0 = TPOS/TDAT and TNEG are sampled on the rising edge of TCLK.

1 = TPOS/TDAT and TNEG are sampled on the falling edge of TCLK.

MOT

Motorola Bus Mode Enable

0 = Intel bus mode

1 = Motorola bus mode

ALE

Address Latch Enable. This signal controls a latch on the A[5:0] inputs. In nonmultiplexed bus

applications, ALE should be wired high to make the latch transparent. In multiplexed bus

applications, A[5:0] should be wired to D[5:0]. The falling edge of ALE latches the address.

Chip Select (Active Low).

CS must be asserted in order to read or write internal registers.

WR / R/W

Write Enable (Active Low) or Read/Write Select. In Intel bus mode (MOT = 0),

WR is asserted to

write internal registers. In Motorola bus mode (MOT = 1), R/

W determines the type of bus

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