DS3151N datasheet(14/61 Pages) MAXIM

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

14 of 61

NAME

I/O

FUNCTION

transaction, with R/

W = 1 indicating a read and R/W = 0 indicating a write.

RD/DS

Read Enable (Active Low) or Data Strobe (Active Low). In Intel bus mode (MOT = 0),

RD is asserted

to read internal registers. In Motorola bus mode (MOT = 1), the rising edge of

DS writes data to

internal registers.

A[5:0]

Address Bus. These inputs specify the address of the internal register to be accessed. A5 is not

present on the DS3152. A5 and A4 are not present on the DS3151.

D[7:0]

I/O

Data Bus. These bidirectional lines are inputs during writes to internal registers. They are outputs

during reads from internal registers.

INT

Interrupt Output (Active Low, Open Drain). This pin is forced low in response to one or more

unmasked, active interrupt sources within the device.

INT remains low until the interrupt is serviced or

masked.

VDD

Positive Supply. 3.3V

±5%. All V

DD signals should be wired together.

VSS

Ground Reference. All VSS signals should be wired together.

Table 4-E. JTAG and Test Pin Descriptions

NAME

I/O

FUNCTION

JTCLK

JTAG IEEE 1149.1 Test Serial Clock. JTCLK shifts data into JTDI on the rising edge and out of

JTDO on the falling edge. If boundary scan is not used, JTCLK should be pulled high.

JTDI

IPU

JTAG IEEE 1149.1 Test Serial-Data Input (Internal 10k

Ω Pullup). Test instructions and data are

clocked in on this pin on the rising edge of JTCLK. If boundary scan is not used, JTDI should be left

unconnected or pulled high.

JTDO

JTAG IEEE 1149.1 Test Serial-Data Output. Test instructions and data are clocked out on this pin on

the falling edge of JTCLK.

JTRST

IPU

JTAG IEEE 1149.1 Test Reset (Internal 10k

Ω Pullup). This pin is used to asynchronously reset the

test access port (TAP) controller. If boundary scan is not used,

JTRST can be held low or high.

JTMS

IPU

JTAG IEEE 1149.1 Test Mode Select (Internal 10k

Ω Pullup). This pin is sampled on the rising edge

of JTCLK and is used to place the port into the various defined IEEE 1149.1 states. If boundary scan

is not used, JTMS should be left unconnected or pulled high.

TEST

IPU

Factory Test Pin. Leave unconnected or wire high for normal operation.

Note 1: Pin type I = input pin. Pin type O = output pin. Pin type P = power-supply pin.

Note 2: Pin type O3 is an output that can be tri-stated.

Note 3: Pin type IPU is an input with an internal 10kΩ pullup.

Note 4: For pin names of the form PINn, n = LIU# = 1, 2, 3, or 4. PIN1 is on LIU 1, PIN2 is on LIU 2, etc.

Note 5: Section 14 shows hardware mode and CPU bus mode pin assignments.

Table 4-F. Transmitter Data Select Options

TDSA

TDSB

E3M

STS

Tx MODE

TRANSMIT DATA SELECTED

Any

Normal data as input at TPOS and TNEG

DS3

STS-1

Unframed all ones

DS3

DS3 AIS per ANSI T1.107 (Figure 7-2)

Any

Unframed 100100… pattern

23 - 1 PRBS pattern per ITU O.151

DS3

STS-1

15 - 1 PRBS pattern per ITU O.151

Note 1: This coding of the TDSA, TDSB, E3M, and STS bits allows AIS generation to be enabled by holding TDSA = 0 and changing TDSB

from 0 to 1. The type of DS3 AIS signal is selected by the STS bit with E3M = 0.

Note 2: If E3M and/or STS are changed when {TDSA,TDSB}

≠ 00, TDSA and TDSB must both be cleared to 0. After they are cleared, TDSA

and TDSB can be configured to transmit a pattern in the new operating mode.

Table 4-G. Receiver PRBS Pattern Select Options

E3M

STS

Rx MODE

RECEIVER PRBS PATTERN SELECTED

23 - 1 PRBS pattern per ITU O.151

DS3

STS-1

15 - 1 PRBS pattern per ITU O.151

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