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MB90F482B 数据表(PDF) 44 Page - fujitsu semiconductor |
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MB90F482B 数据表(HTML) 44 Page - fujitsu semiconductor |
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44 / 124 page  MB90480B/485B Series 44 DS07-13722-11E (2) Block Diagram • 8-bit PPG ch.0/2/4 block Diagram S R Q PRLBH PRLL PRLH PPG0/2/4 PEN0 IRQ PIE0 PUF0 Peripheral clock × 16 Peripheral clock × 8 Peripheral clock × 4 Peripheral clock × 2 Peripheral clock Count clock select Timebase counter output main clock × 512 PCNT (down counter) “L”/“H” selector PPG0/2/4 output enable A/D converter PPG0/2/4 output latch ch.1/3/5 borrow “L” data bus “H” data bus PPGC0 (operation mode control) “L”/“H” select |
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