PCF8532 datasheet(21/44 Pages) NXP

21 / 44 page

PCF8532_1

Product data sheet

Rev. 1 — 10 February 2009

21 of 44

NXP Semiconductors

PCF8532

Universal LCD driver for low multiplex rates

7.16.6 Input ﬁlters

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

7.16.7 I2C-bus protocol

Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8532.

The least signiﬁcant bit of the slave address that a PCF8532 responds to is deﬁned by the

level tied at its input SA0. The PCF8532 is a write only device and does not respond to a

read access. Two types of PCF8532 can be distinguished on the same I2C-bus which

allows:

• Up to 8 PCF8532’s on the same I2C-bus for very large LCD applications

• The use of two types of LCD multiplex on the same I2C-bus.

The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of the two PCF8532 slave

addresses available. All PCF8532’s with the corresponding SA0 level acknowledge in

parallel to the slave address, but all PCF8532’s with the alternative SA0 level ignore the

whole I2C-bus transfer.

After acknowledgement, a control byte follows which deﬁnes if the next byte is RAM or

command information. The control byte also deﬁnes if the next following byte is a control

byte or further RAM/command data.

In this way it is possible to conﬁgure the device then ﬁll the display RAM with little

overhead.

The command bytes and control bytes are also acknowledged by all addressed

PCF8532’s connected to the bus.

The display bytes are stored in the display RAM at the address speciﬁed by the data

pointer and the subaddress counter. Both data pointer and subaddress counter are

automatically updated and the data is directed to the intended PCF8532 device.

The acknowledgement after each byte is made only by the (A0 and A1) addressed

PCF8532. After the last (display) byte, the I2C-bus master issues a STOP condition (P).

Alternatively a START may be issued to RESTART an I2C-bus access.

PCF8532 数据表(PDF) 21 Page - NXP Semiconductors

PCF8532 数据表(HTML) 21 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载