PCF8532 datasheet(13/44 Pages) NXP

13 / 44 page

PCF8532_1

Product data sheet

Rev. 1 — 10 February 2009

13 of 44

NXP Semiconductors

PCF8532

Universal LCD driver for low multiplex rates

7.5 Oscillator

The internal logic and the LCD drive signals of the PCF8532 are timed by a frequency fclk

which either is derived from the built-in oscillator frequency fosc (

) or equals an

external clock frequency fclk(ext) ().

The clock frequency fclk determines the LCD frame frequency ffr (see Table 15).

7.5.1 Internal clock

The internal logic and the LCD drive signals of the PCF8532 are timed either by the

built-in oscillator or by an external clock.

The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case the output

from pin CLK provides the clock signal for cascaded PCF8532’s in the system. However,

the clock signal is only available at the pin CLK, if the display is enabled. The display is

enabled using the display enable bit (see Table 9).

The nominal output clock frequency is like speciﬁed in Table 18 with parameter fclk.

7.5.2 External clock

Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the

external clock input.

A clock signal must always be supplied to the device; removing the clock may freeze the

LCD in a DC state.

7.6 Timing and frame frequency

The timing of the PCF8532 organizes the internal data ﬂow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs.

In cascaded applications, the synchronization signal (SYNC) maintains the correct timing

relationship between all the PCF8532’s in the system.

The clock frequency can be programmed by software such that the nominal frame

frequency can be chosen in steps of 5 Hz in the range of 60 Hz to 90 Hz (see Table 15).

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display register, the

LCD segment outputs and one column of the display RAM.

7.8 Segment outputs

The LCD drive section includes 160 segment outputs (S0 to S159) which must be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data residing in the display register. When

less than 160 segment outputs are required the unused segment outputs must be left

open-circuit.

clk

osc

----------

clk

clk ext

(

)

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