M95128-RMB6GSLASHP datasheet(19/44 Pages) STMICROELECTRONICS

19 / 44 page

M95128, M95128-W, M95128-R

Instructions

Doc ID 5798 Rev 13

19/44

The protection features of the device are summarized in Table 2.

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless

of whether Write Protect (W) is driven high or low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W):

●

If Write Protect (W) is driven high, it is possible to write to the Status Register provided

that the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction.

●

If Write Protect (W) is driven low, it is not possible to write to the Status Register even if

the Write enable Latch (WEL) bit has previously been set by a Write Enable (WREN)

instruction. (Attempts to write to the Status Register are rejected, and are not accepted

for execution.) As a consequence, all the data bytes in the memory area that are

software-protected (SPM) by the Block protect (BP1, BP0) bits in the Status Register,

are also hardware-protected against data modification.

Regardless of the order of the two events, the Hardware-protected mode (HPM) can be

entered:

●

by setting the Status register write disable (SRWD) bit after driving Write Protect (W)

low

●

or by driving Write Protect (W) low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware-protected mode (HPM) once entered is to pull Write

Protect (W) high.

If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can

never be activated, and only the Software-protected mode (SPM), using the Block protect

(BP1, BP0) bits in the Status Register, can be used.

Figure 8.

Write Status Register (WRSR) sequence

AI02282D

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High Impedance

Instruction

Status

765432

MSB

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