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M24C32-R 数据表(PDF) 26 Page - STMicroelectronics

部件名 M24C32-R
功能描述  32 Kbit serial I²C bus EEPROM
PDF  38 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M24C32-R 数据表(HTML) 26 Page - STMicroelectronics

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DC and AC parameters
M24C32-W M24C32-R M24C32-F
26/38
Doc ID 4578 Rev 17
Table 16.
AC characteristics
Test conditions specified in Table 7, Table 8 and Table 9
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock frequency
400
kHz
tCHCL
tHIGH
Clock pulse width high
600
ns
tCLCH
tLOW
Clock pulse width low
1300
ns
tQL1QL2
(1)
1.
Characterized only, not tested in production.
tF
SDA (out) fall time
20(2)
2.
With CL = 10 pF.
120
ns
tXH1XH2
tR
Input signal rise time
(3)
3.
There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
(3)
ns
tXL1XL2
tF
Input signal fall time
(3)
(3)
ns
tDXCX
tSU:DAT Data in set up time
100
ns
tCLDX
tHD:DAT Data in hold time
0
ns
tCLQX
tDH
Data out hold time
200
ns
tCLQV
(4)(5)
4.
To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5.
tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 4.
tAA
Clock low to next data valid (access time)
200
900
ns
tCHDL
tSU:STA Start condition setup time
600
ns
tDLCL
tHD:STA Start condition hold time
600
ns
tCHDH
tSU:STO Stop condition set up time
600
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
ns
tW
tWR
Write time
5
ms



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