AD9552PCBZ datasheet(6/32 Pages) AD

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AD9552

Rev. C | Page 6 of 32

SERIAL CONTROL PORT

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Input Logic 1 Voltage

1.6

Input Logic 0 Voltage

0.5

Input Logic 1 Current

0.03

μA

Input Logic 0 Current

μA

Input Capacitance

SCLK

Input Logic 1 Voltage

1.6

Input Logic 0 Voltage

0.5

Input Logic 1 Current

μA

Input Logic 0 Current

0.03

μA

Input Capacitance

SDIO

Input

Input Logic 1 Voltage

1.6

Input Logic 0 Voltage

0.5

Input Logic 1 Current

μA

Input Logic 0 Current

μA

Input Capacitance

Output

Output Logic 1 Voltage

2.8

1 mA load current

Output Logic 0 Voltage

0.3

1 mA load current

SERIAL CONTROL PORT TIMING

Table 6.

Parameter

Limit

Unit

SCLK

Clock Rate, 1/tCLK

MHz max

Pulse Width High, tHIGH

ns min

Pulse Width Low, tLOW

ns min

SDIO to SCLK Setup, tDS

ns min

SCLK to SDIO Hold, tDH

ns min

SCLK to Valid SDIO, tDV

ns max

CS to SCLK Setup (tS) and Hold (tH)

ns min

CS Minimum Pulse Width High

6.4

ns min

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