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AD9552PCBZ 数据表(PDF) 3 Page - Analog Devices

部件名 AD9552PCBZ
功能描述  Oscillator Frequency Upconverter
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9552PCBZ 数据表(HTML) 3 Page - Analog Devices

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AD9552
Rev. C | Page 3 of 32
SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for VDD = 3.3 V; TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY VOLTAGE
3.135
3.30
3.465
V
Pin 7, Pin 18, Pin 21, Pin 28
POWER CONSUMPTION
Total Current
149
169
mA
At maximum output frequency with both output channels active
VDD Current By Pin
Pin 7
2
3
mA
Pin 18
77
86
mA
Pin 21
35
41
mA
Pin 28
35
41
mA
LVPECL Output Driver
36
41
mA
900 MHz with 100 Ω termination between both pins of the output
driver
LOGIC INPUT PINS
INPUT CHARACTERISTICS1
Logic 1 Voltage, VIH
1.0
V
For the CMOS inputs, a static Logic 1 results from either a pull-up
resistor or no connection
Logic 0 Voltage, VIL
0.8
V
Logic 1 Current, IIH
3
μA
Logic 0 Current, IIL
17
μA
LOGIC OUTPUT PINS
Output Characteristics
Output Voltage High, VOH
2.7
V
Output Voltage Low, VOL
0.4
V
RESET PIN
Input Characteristics2
Input Voltage High, VIH
1.8
V
Input Voltage Low, VIL
1.3
V
Input Current High, IINH
0.3
12.5
μA
Input Current Low, IINL
31
43
μA
Minimum Pulse Width High
2
ns
REFERENCE CLOCK
INPUT CHARACTERISTICS
Frequency Range
7.94
MHz
N3 = 255; 2× frequency multiplier enabled; valid for all VCO bands
6.57
MHz
N3 = 255; 2× frequency multiplier enabled; fVCO = 3.35 GHz, which con-
strains the frequency at OUT1 to be an integer sub-multiple of 3.35 GHz
(that is, fOUT1 = 3.35 ÷ M GHz, where M is the product of the P0 and P1
output divider values)
93.06
MHz
SDM4 disabled; N3 = 365; valid for all VCO bands
71.28
MHz
SDM4 enabled; N3 = 476; valid for all VCO bands
112.5
MHz
SDM4 disabled; N3 = 365; fVCO = 4.05 GHz, which constrains the
frequency at OUT1 to be an integer sub-multiple of 4.05 GHz (that is,
fOUT1 = 4.05÷M GHz, where M is the product of the P0 and P1 output
divider values)
86.17
MHz
SDM4 enabled; N3 = 476; fVCO = 4.05 GHz, which constrains the frequency
at OUT1 to be an integer sub-multiple of 4.05 GHz (that is, fOUT1 =
4.05÷M GHz, where M is the product of the P0 and P1 output divider
values)



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