M41ST87YSS6 datasheet(22/52 Pages) STMICROELECTRONICS

22 / 52 page

Operating modes

M41ST87Y, M41ST87W

22/52

Doc ID 9497 Rev 8

2.6.6

Tamper detect sampling (TDS1 and TDS2)

This bit selects between a 1Hz sampling rate or constant monitoring of the tamper input

pin(s) to detect a tamper event when the normally closed switch mode is selected. This

allows the user to reduce the current drain when the TEBX bit is enabled while the device is

in battery backup (see Table 4 on page 23 and Figure 17 on page 23). Sampling is disabled

if the TCMX bit is set to logic '1' (Normally Open). In this case the state of the TDSX bit is a

“Don’t care.”

Note:

The crystal oscillator must be “on” for sampling to function. If the oscillator is stopped, the

tamper detect circuit will revert to continuous monitoring.

2.6.7

Tamper current high/tamper current low (TCHI/TCLO1 and

TCHI/TCLO2)

This bit selects the strength of the internal pull-up or pull-down used during the sampling of

the normally closed condition. The state of the TCHI/TCLOX bit is a “Don’t care” for normally

open (TCMX = '1') mode (see Figure 18 on page 24).

2.6.8

RAM clear (CLR1 and CLR2)

When either CLR1 or CLR2 and the TEBX bit are set to a logic '1,' the internal 128 bytes of

user RAM (see Figure 15 on page 21) will be cleared to all zeros in the event of a tamper

condition. Furthermore, the 128 bytes of user RAM will be deselected (inaccessible) until

the corresponding TEBX bit is reset to '0.' Any data read during this time will be invalid. (ie.

the cleared RAM values cannot be accessed.)

2.6.9

RAM clear external (CLR1EXT and CLR2EXT) - available in SOX28

package only

When either CLR1EXT or CLR2EXT is set to a logic '1' and the TEBX bit is also set to logic '1,'

the TPCLR signal will be asserted for clearing external RAM, and the RST output asserted

upon detection of a tamper event (see Figure 15 on page 21 and Figure 20 on page 25).

Note:

The reset output resulting from a tamper event will be the same as a reset resulting from a

power-down condition, a watchdog time-out, or a manual reset (RSTIN1 or RSTIN2); the

RST output will be asserted for trec seconds.

This is accomplished by forcing TPCLR high, which if used to control the inhibit pin of the DC

regulator (see Figure 20 on page 25) will also switch off VOUT, depriving the external SRAM

of power to the VCC pin. VOUT will automatically be disconnected from the battery if the

tamper occurs during battery back-up (see Figure 19 on page 24). By inhibiting the DC

regulator, the user will also prevent other inputs from sourcing current to the external SRAM,

which would allow it to retain data otherwise.

The user may optionally connect an inverting charge pump to the VCC pin of the external

SRAM (see Figure 20 on page 25). Depending on the process technology used for the

manufacturing of the external SRAM, clearing the memory may require varying durations of

negative potential on the VCC pin. This device configuration will allow the user to program

the time needed for their particular application. Control Bits CLRPW0 and CLRPW1

determine the duration TPCLR will be enabled (see Figure 19 on page 24 and Table 5 on

page 25).

Note:

When using the inverting charge pump, the user must also provide isolation in the form of

two additional small-signal power MOSFETs. These will isolate the VOUT pin from both the

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