L9950 datasheet(7/39 Pages) STMICROELECTRONICS

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L9950 - L9950XP

Block diagram and pin description

Doc ID 10311 Rev 10

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OUT1

OUT2

OUT3

Hal bridge output 1,2,3.

The output is built by a highside and a lowside switch, which are

internally connected. The output stage of both switches is a power

DMOS transistor. Each driver has an internal parasitic reverse diode

(bulk-drain-diode: highside driver from output to VS, lowside driver from

GND to output). This output is over-current and open load protected.

6, 7, 14, 15,

23, 24, 25, 28,

29, 32

Power supply voltage (external reverse protection required.

For this input a ceramic capacitor as close as possible to GND is

recommended.

Important: for the capability of driving the full current at the outputs all

pins of VS must be externally connected.

8DI

Serial data input.

The input requires CMOS logic levels and receives serial data from the

microcontroller. The data is an 24bit control word and the least

significant bit (LSB, bit 0) is transferred first.

CM/PWM2

Current monitor output/PWM2 input.

Depending on the selected multiplexer bits of Input Data Register this

output sources an image of the instant current through the

corresponding highside driver with a ratio of 1/10.000. This pin is

bidirectional. The microcontroller can overdrive the current monitor

signal to provide a second PWM input for the outputs OUT9 and

OUT10.

CSN

Chip select not input/test mode.

This input is low active and requires CMOS logic levels. The serial data

transfer between L9950 and micro controller is enabled by pulling the

input CSN to low level. If an input voltage of more than 7.5V is applied

to CSN pin the L9950 will be switched into a test mode.

Serial data output.

The diagnosis data is available via the SPI and this tristate output. The

output will remain in tristate, if the chip is not selected by the input CSN

(CSN = high).

VCC

Logic supply voltage.

For this input a ceramic capacitor as close as possible to GND is

recommended.

CLK

Serial clock input.

This input controls the internal shift register of the SPI and requires

CMOS logic levels.

16,17, 20,21,

OUT4

OUT5

OUT6

Half bridge output 4,5,6: see OUT1 (pin 3).

Important: for the capability of driving the full current at the outputs both

pins of OUT4 (OUT5, respectively) must be externally connected.

Charge pump output.

This output is provided to drive the gate of an external n-channel power

MOS used for reverse polarity protection

Table 2.

Pin definitions and functions (continued)

Symbol

Function

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