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L9950 数据表(PDF) 16 Page - STMicroelectronics

部件名 L9950
功能描述  Door actuator driver
PDF  39 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L9950 数据表(HTML) 16 Page - STMicroelectronics

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Electrical specifications
L9950 - L9950XP
16/39
Doc ID 10311 Rev 10
Figure 3.
SPI - transfer timing diagram
Table 16.
DO timing
Symbol
Parameter
Test condition
Min.
Typ. Max. Unit
tr DO
DO rise time
CL = 100 pF, Iload = -1 mA
-
80
140
ns
tf DO
DO fall time
CL = 100 pF, Iload = 1 mA
-
50
100
ns
ten DO tri L
DO enable time
from tristate to low level
CL = 100 pF, Iload = 1 mA
pull-up load to VCC
-
100
250
ns
tdis DO L tri
DO disable time
from low level to tristate
CL = 100 pF, Iload = 4 mA
pull-up load to VCC
-
380
450
ns
ten DO tri H
DO enable time
from tristate to high level
CL =100 pF, Iload = -1 mA
pull-down load to GND
-
100
250
ns
tdis DO H tri
DO disable time
from high level to tristate
CL = 100 pF, Iload = -4 mA
pull-down load to GND
-
380
450
ns
td DO
DO delay time
VDO < 0.3 VCC, VDO > 0.7 VCC,
CL = 100 pF
-50
250
ns
Table 17.
CSN timing
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tCSN_HI,stb
Minimum CSN HI time,
switching from standby mode
Transfer of SPI command
to Input Register
-20
50
µs
tCSN_HI,min
Maximum CSN HI time,
active mode
Transfer of SPI command
to input register
-2
4
µs
1
2
34
56
7
0
01
12
3
45
67
0
12
3
4
5
6
7
0
0
1
01
CSN
CLK
DI
DO
Input
Data
Register
CSN high to low: DO enabled
time
DI: data will be accepted on the rising edge of CLK signal
time
time
time
time
DO: data will change on the falling edge of CLK signal
fault bit
CSN low to high: actual data is
transfered to output power switches
old data
new data
23
22
21
20
19
18
23
22
21
20
19
18
23
22
21
20
19
18
X
X
X
X
X
X
1
2
34
56
7
0
01
12
3
45
67
0
1
2
34
56
7
0
01
12
3
45
67
0
12
3
4
5
6
7
0
0
1
01
CSN
CLK
DI
DO
Input
Data
Register
CSN high to low: DO enabled
time
DI: data will be accepted on the rising edge of CLK signal
time
time
time
time
DO: data will change on the falling edge of CLK signal
fault bit
CSN low to high: actual data is
transfered to output power switches
old data
new data
12
3
4
5
6
7
0
0
1
01
CSN
CLK
DI
DO
Input
Data
Register
CSN high to low: DO enabled
time
DI: data will be accepted on the rising edge of CLK signal
time
time
time
time
DO: data will change on the falling edge of CLK signal
fault bit
CSN low to high: actual data is
transfered to output power switches
old data
new data
23
22
21
20
19
18
23
22
21
20
19
18
23
22
21
20
19
18
X
X
X
X
X
X



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