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14

Data Sheet

Differential Input

Voltage

(IP - IN)

Output data: D_11:

(2’s Complement)

Out of Range

(Use Logical AND Function for &)

Output Data: D_11:

(2’s Complement)

Out of Range

(Use Logical AND Function for &)

> 0.5V

0111 1111 1111

D_12 = 1 & D_11 = 1

0111 1111 1111

D_12 = 0 & D_11 = 1

0.5V

0111 1111 1111

0111 1111 1111

+0.24mV

0000 0000 0000

0000 0000 0000

-0.24mV

1111 1111 1111

1111 1111 1111

-0.5V

1000 0000 0000

1000 0000 0000

< -0.5V

1000 0000 0000

D_12 = 0 & D_11 = 0

1000 0000 0000

D_12 = 1 & D_11 = 0

Reference Voltages

The reference voltages are internally generated and buff-

ered based on a bandgap voltage reference. No external

decoupling is necessary, and the reference voltages are

not available externally. This simplifies usage of the ADC

since two extremely sensitive pins, otherwise needed, are

removed from the interface.

If a lower full scale range is required the 13-bit output

word provides sufficient resolution to perform digital scaling

with an equivalent impact on noise compared to adjusting

the reference voltages.

output word is shown in the Table 2 below. Note that only

2‘s complement output data are available in this mode

and that out of range conditions must be determined

based on a two bit output. The output code will wrap

around when the code goes outside the full scale range.

The out of range bits should be used to clamp the output

data for overrange conditions.

Operational Modes

The operational modes are controlled with the PD_N and

SLP_N pins. If PD_N is set low, all other control pins are

overridden and the chip is set in Power Down mode. In

this mode all circuitry is completely turned off and the

internal clock is disabled. Hence, only leakage current

contributes to the Power Down Dissipation. The startup

time from this mode is longer than for other idle modes

as all references need to settle to their final values before

normal operation can resume.

The SLP_N bus can be used to power down each channel

independently, or to set the full chip in Sleep Mode. In this

mode internal clocking is disabled, but some low band-

width circuitry is kept on to allow for a short startup time.

However, Sleep Mode represents a significant reduction in

supply current, and it can be used to save power even for

short idle periods.

The input clock could be kept running in all idle modes.

However, even lower power dissipation is possible in

Power Down mode if the input clock is stopped. In this

case it is important to start the input clock prior to en-

abling active mode.

Differential Input Voltage (IP - IN)

Output data: D_12 : D_0

(DFRMT = 0, offset binary)

Output Data: D_12 : D_0

(DFRMT = 1, 2’s complement)

1.0 V

1 1111 1111 1111

0 1111 1111 1111

+0.24mV

1 0000 0000 0000

0 0000 0000 0000

-0.24mV

0 1111 1111 1111

1 1111 1111 1111

-1.0V

0 0000 0000 0000

1 0000 0000 0000