Pin descriptions

STM706T/S/R, STM706P, STM708T/S/R

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Doc ID 10518 Rev 10

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Pin descriptions

2.1

MR

A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low

driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if

unused.

2.2

WDI

If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset (or

WDO) is triggered. The internal watchdog timer clears while reset is asserted or when WDI

sees a rising or falling edge.

The watchdog function cannot be disabled by allowing the WDI pin to float.

2.3

WDO

WDO goes low when a transition does not occur on WDI within 1.6 s, and remains low until

a transition occurs on WDI (indicating the watchdog interrupt has been serviced). WDO also

Note:

For those devices with a WDO output, a watchdog timeout will not trigger reset unless WDO

is connected to MR.

2.4

RST

reset threshold, the watchdog triggers a reset, or MR goes from low to high.

2.5

RST

reset threshold, the watchdog triggers a reset, or MR goes from high to low.

2.6

PFI

ground if unused.