Data Sheet

©2004-2008 CADEKA Microcircuits LLC

www.cadeka.com

13

Application Information

Basic Operation

Figures 1 and 2 illustrate typical circuit configurations for

non-inverting, inverting, and unity gain topologies for dual

supply applications. They show the recommended bypass

capacitor values and overall closed loop gain equations.

+

-

0.1μF

6.8μF

Output

Input

0.1μF

6.8μF

Figure 1. Typical Non-Inverting Gain Circuit

Figure 2. Typical Inverting Gain Circuit

Power Supply and Decoupling

The CLC2000 can be powered with a low noise supply

anywhere in the range from +5V to +13V. Ensure ad-

equate metal connections to power pins in the PC board

layout with careful attention paid to decoupling the power

supply.

High quality capacitors with low equivalent series resis-

tance (ESR) such as multilayer ceramic capacitors (MLCC)

should be used to minimize supply voltage ripple and

power dissipation.

Two decoupling capacitors should be placed on each pow-

er pin with connection to a local PC board ground plane.

A large, usually tantalum, 10μF to 47μF capacitor is re-

quired to provide good decoupling for lower frequency

signals and to provide current for fast, large signal chang-

es at the CLC2000 outputs. It should be within 0.25” of

the pin. A secondary smaller 0.1μF MLCC capacitor should

located within 0.125” to reject higher frequency noise on

the power line.

Power Dissipation

Power dissipation is an important consideration in applica-

tions with low impedance DC, coupled loads. Guidelines

listed below can be used to verify that the particular ap-

plication will not cause the device to operate beyond its

intended operating range. Calculations below relate to a

single amplifier. For the CLC2000, both amplifiers power

contribution needs to be added for the total power dis-

sipation.

Maximum power levels are set by the absolute maximum

junction rating of 150°C. To calculate the junction tem-

ment.

needs to be subtracted from the total power delivered by

the supplies.

Supply power is calculated by the standard power equa-

tion.

Power delivered to a purely resistive load is:

The effective load resistor will need to include the effect

of the feedback network. For instance,

+

-

0.1μF

6.8μF

Output

For optimum input offset

Input

0.1μF

6.8μF