Data Sheet

©2004-2008 CADEKA Microcircuits LLC

www.cadeka.com

14

These measurements are basic and are relatively easy to

perform with standard lab equipment. For design purposes

however, prior knowledge of actual signal levels and load

impedance is needed to determine the dissipated power.

can be calculated as above with the desired signal ampli-

tudes using:

The dynamic power is focused primarily within the output

stage driving the load. This value can be calculated as:

Assuming the load is referenced in the middle of the pow-

Figure 3 shows the maximum safe power dissipation in

the package vs. the ambient temperature for the 8 Lead

SOIC packages.

0

0.5

1

1.5

2

2.5

-40

-20

0

20

40

60

80

Ambient Temperature (°C)

SOIC-8

Figure 3. Maximum Power Derating

Better thermal ratings can be achieved by maximizing

PC board metallization at the package pins. However, be

careful of stray capacitance on the input pins.

In addition, increased airflow across the package can also

In the event of a short circuit condition, the CLC2000 has

circuitry to limit output drive capability to ±1000mA. This

will only protect against a momentary event. Extended

duration under these conditions will cause junction tem-

peratures to exceed 150°C. Due to internal metallization

constraints, continuous output current should be limited

to ±100mA.

Driving Capacitive Loads

Increased phase delay at the output due to capacitive load-

ing can cause ringing, peaking in the frequency response,

and possible unstable behavior. Use a series resistance,

stability and settling performance. Refer to Figure 4.

+

-

Input

Output

Capacitive Loads

peaking in the frequency response. The Frequency Re-

the CLC2000.

-3dB BW (MHz)

10

40

275

20

24.5

250

50

20

175

100

13.5

135

500

6

75

1000

5

45

tradeoff between settling time and bandwidth. In general,

ditional overshoot and ringing.