STCD1020 datasheet(13/40 Pages) STMICROELECTRONICS

13 / 40 page

STCD1020, STCD1030, STCD1040

Application information

Doc ID 13823 Rev 6

13/40

Figure 8.

Typical application circuit using STCD1040 for baseband peripherals in

mobile phone

4.2

Connection of the source clock to MCLK

If the output of the clock source voltage level is within the supply rails of the STCD1020,

STCD1030 and STCD1040, the output of the source clock should be connected directly to

the MCLK of the clock distribution circuits. This is described in Figure 9. The direct

connection of the source clock is the common case and a DC-CUT capacitor is saved on

PCB.

Figure 9.

Direct connection of the source clock

Note:

The input clock voltage level of the STCD1020, STCD1030, and STCD1040 cannot exceed

the supply rails when it is directly connected to the source clock. If it is needed to connect a

source clock with the voltage level exceeds the supply rails of the clock distribution circuits,

the user needs to connect a DC-CUT capacitor serially as shown in Figure 10. A voltage

divider formed by a resistor string is also needed to set a proper DC bias for the clock input

GND

CLK1

EN1

CLK2

EN2

CLK3

EN3

CLK4

VCC

BT_External_Req

VCC

MCLK

VCTCXO

STCD1040 EN4

Bluetooth

WLAN

GPS

Other

device

ai13955

STCD1020

STCD1030

STCD1040

VCTCXO

MCLK

OUT

VCC

ai13956

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