STCD1020, STCD1030, STCD1040

DC and AC parameters

Doc ID 13823 Rev 6

17/40

Additive phase noise(3)(8)

at 1 kHz offset

–135

dBc/

Hz

at 10 kHz offset

–145

at 100 kHz offset

–150

Buffer recovery time from off to on

STCD10x0 active

20

µs

STCD10x0 active recovery time

from standby to active

50

µs

Capacitive load for each channel

10

20

pF

Resistive load for each channel

10

k

Ω

1.

Load capacitance = 10 pF (except where noted).

2.

Clock input voltage level should not exceed supply rails.

3.

Simulated and determined via design and NOT 100% tested.

4.

The quiescent current is measured when the enable pins are active, but without input master clock signal (fmclk = 0 Hz).

5.

The active current is dependent on the master clock input Vpp and frequency and the capacitive load condition. The typical

6.

7.

8.

Guaranteed with the supply noise of 30 µ Vrms from 300 Hz to 50 kHz.

Table 7.

DC and AC characteristics (1.8 V supply)

Symbol

Parameter

Min

Typ

Max

Unit

Table 8.

Operating and AC measurement conditions (2.8 V supply)

Parameter

Condition

Unit

2.5 to 3.6

V

Output clock voltage (CLK1…CLK4)

V

Device enable voltage (EN1…EN4)

V

–40 to +85

Table 9.

DC and AC characteristics (2.8 V supply)

Symbol

Parameter

Min

Typ

Max

Unit

Master clock (eg. from VCTCXO)

Sine wave/square wave

10

26

52

MHz

Supply voltage

2.5

2.8

3.6

V

Vin

0.75

1

Vpp

Vout

–1.5

–0.5

dB

2 buffers version

1.7

2.6

mA

3 buffers version

2.2

3.3

4 buffers version

2.8

4