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The inductance must be sufficiently large to allow the PFC controller IC1 to maintain stable

operation when the line input at maximum and the dimming level is at minimum. Under these conditions

the COMP voltage at pin 2 will be very low and the PWM on time will be very short. If the inductor value

is too small the on time will become too small for the control IC to be able to maintain a stable DC bus.

The result of an unstable DC bus is a slight but visible flicker seen when the lamp is dimmed.

Such instability is usually caused by instability of the power factor correction section rather than the lamp

current regulation loop incorporated within the IRS2158D (IC2).

The trade off is that if the value of LPFC is too high the bus voltage will start to drop at low line

input and maximum load since the COMP pin voltage has reached maximum and therefore the maximum

on time limit has been reached. The lamp current control loop is however able to lower the ballast

frequency in order to compensate for this to some degree if necessary.

PCB Layout Considerations

In order to successfully utilize the IRS2158D in a ballast design, it is necessary to follow the

following PCB layout guidelines. This can avoid possible interference and ground loop issues that can

occur in the ballast circuit. These connection techniques also prevent high current ground loops from

interfering with sensitive timing component operation, and allows the entire control circuit to reject

common-mode noise due to output switching.

Figure 14 and Figure 15 show the control section of a typical ballast designed around the

IRS2158D, where the IC is located in the center. In this design all SMD devices are mounted under the

PCB with discrete devices on top.

Fig 14. Critical traces on the bottom side of the PCB

Fig 15. Critical traces on the top side of the PCB