P89LPC922A1FDH datasheet(39/75 Pages) NXP

39 / 75 page

P89LPC92X1

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Product data sheet

Rev. 2 — 1 December 2010

39 of 75

NXP Semiconductors

P89LPC9201/9211/922A1/9241/

8-bit microcontroller with 8-bit ADC

7.22.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the TI interrupt is generated

when the double buffer is ready to receive new data.

7.22.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long

as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until

the bit is shifted out, as indicated by the TI interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will

be double-buffered together with SBUF data.

7.23 I2C-bus serial interface

The I2C-bus uses two wires (SDA and SCL) to transfer information between devices

connected to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves

• Multi master bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I2C-bus may be used for test and diagnostic purposes.

A typical I2C-bus configuration is shown in Figure 11. The

P89LPC9201/9211/922A1/9241/9251 device provides a byte-oriented I2C-bus interface

that supports data transfers up to 400 kHz.

Fig 11. I2C-bus configuration

OTHER DEVICE

WITH I2C-BUS

INTERFACE

SDA

SCL

OTHER DEVICE

WITH I2C-BUS

INTERFACE

P1.3/SDA

P1.2/SCL

P89LPC9201/9211/

922A1/9241/9251

I2C-bus

002aae430

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