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ADSP-21469KBZ-ENG2 数据表(PDF) 49 Page - Analog Devices |
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ADSP-21469KBZ-ENG2 数据表(HTML) 49 Page - Analog Devices |
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49 / 56 page  ADSP-21469/ADSP-21469W Preliminary Technical Data Rev. PrB | Page 49 of 56 | November 2008 JTAG Test Access Port and Emulation Table 46. JTAG Test Access Port and Emulation Parameter Min Max Unit Timing Requirements tTCK TCK Period TBD TBD ns tSTAP TDI, TMS Setup Before TCK High TBD TBD ns tHTAP TDI, TMS Hold After TCK High TBD TBD ns tSSYS 1 System Inputs Setup Before TCK High TBD TBD ns tHSYS 1 System Inputs Hold After TCK High TBD TBD ns tTRSTW TRST Pulse Width TBD TBD ns Switching Characteristics TBD TBD tDTDO TDO Delay from TCK Low TBD TBD ns tDSYS 2 System Outputs Delay After TCK Low TBD TBD ns 1 System Inputs = AD15–0, CLKCFG1–0, RESET, BOOTCFG1–0, DAI_Px, and FLAG3–0. 2 System Outputs = DAI_Px, AD15–0, AMI_RD, AMI_WR, FLAG3–0, CLKOUT, EMU, and ALE. Figure 38. IEEE 1149.1 JTAG Test Access Port TCK TMS TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS tSTAP tTCK tHTAP tDTDO tSSYS tHSYS tDSYS |
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