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AD8375ACPZ-R7 数据表(PDF) 17 Page - Analog Devices

部件名 AD8375ACPZ-R7
功能描述  Ultralow Distortion IF VGA
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8375ACPZ-R7 数据表(HTML) 17 Page - Analog Devices

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AD8375
Rev. 0 | Page 17 of 24
LAYOUT CONSIDERATIONS
There are two output pins for each polarity, and they are
oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
A good practice is to avoid any ground or power plane under
this routing region and under the chokes to minimize the
parasitic capacitance.
CHARACTERIZATION TEST CIRCUITS
Differential-to-Differential Characterization
The S-parameter characterization for the AD8375 was
performed using a dedicated differential input to differential
output characterization board. Figure 44 shows the layout of
characterization board. The board was designed for optimum
impedance matching into a 75 Ω system. Because both the
input and output impedances of the AD8375 are 150 Ω
differentially, 75 Ω impedance runs were used to match 75 Ω
network analyzer port impedances. On-board 1 μH inductors
were used for output biasing, and the output board traces were
designed for minimum capacitance.
0.1µF
0.1µF
L1
1µH
L2
1µH
0.1µF
0.1µF
+5V
5
A0 TO A4
AC
75Ω TRACES
75Ω TRACES
75Ω
75Ω
75Ω
75Ω
AC
AD8375
Figure 42. Test Circuit for S-Parameters on Dedicated 75 Ω
Differential-to-Differential Board
0.1µF
0.1µF
TC3-1T
T1
0.1µF
0.1µF
330Ω
330Ω
25Ω
25Ω
50Ω
+9V
5
A0 TO A4
50Ω
96Ω
96Ω
AC
AD8375
Figure 43. Test Circuit for Time Domain Measurements
Figure 44. Differential-to-Differential Characterization Board
Circuit Side Layout
C1
0.1µF
C2
0.1µF
TC3-1T
AD8375
T1
L1
1µH
L2
1µH
C3
0.1µF
C4
0.1µF
R1
62Ω
R2
62Ω
R4
25Ω
R3
25Ω
ETC1-1-13
T2
50Ω
PAD LOSS = 11dB
+5V
5
A0 TO A4
50Ω
AC
Figure 45. Test Circuit for Distortion, Gain, and Noise



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