M48Z02 datasheet(10/21 Pages) STMICROELECTRONICS

10 / 21 page

Operation modes

M48Z02, M48Z12

10/21

Doc ID 2420 Rev 7

Table 4.

Write mode AC characteristics

2.3

Data retention mode

With valid VCC applied, the M48Z02/12 operates as a conventional BYTEWIDE™ static

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write

protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs

become high impedance, and all inputs are treated as “don't care.”

Note:

A power failure during a WRITE cycle may corrupt data at the currently addressed location,

but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the

user can be assured the memory will be in a write protected state, provided the VCC fall time

is not less than tF. The M48Z02/12 may respond to transient noise spikes on VCC that reach

into the deselect window during the time the device is sampling VCC. Therefore, decoupling

of the power supply lines is recommended.

The power switching circuit connects external VCC to the RAM and disconnects the battery

when VCC rises above VSO. As VCC rises, the battery voltage is checked. If the voltage is

too low, an internal Battery Not OK (BOK) flag will be set. The BOK flag can be checked

after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is

automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 7

on page 11 illustrates how a BOK check routine could be structured.

For more information on a battery storage life refer to the application note AN1012.

Symbol

Parameter(1)

Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where

noted).

M48Z02/M48Z12

Unit

–70

–150

–200

Min

Max

Min

Max

Min

Max

tAVAV

WRITE cycle time

150

200

tAVWL

Address valid to WRITE enable low

tAVEL

Address valid to chip enable 1 low

tWLWH

WRITE enable pulse width

120

tELEH

Chip enable low to chip enable 1 high

120

tWHAX

WRITE enable high to address transition

tEHAX

Chip enable high to address transition

tDVWH

Input valid to WRITE enable high

tDVEH

Input valid to chip enable high

tWHDX

WRITE enable high to input transition

tEHDX

Chip enable high to input transition

tWLQZ

WRITE enable low to output Hi-Z

tAVWH

Address valid to WRITE enable high

120

140

tAVEH

Address valid to chip enable high

120

140

tWHQX

WRITE enable high to output transition

M48Z02 数据表(PDF) 10 Page - STMicroelectronics

M48Z02 数据表(HTML) 10 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

数据表下载