AD7466BRT-R datasheet(21/28 Pages) AD

21 / 28 page

AD7466/AD7467/AD7468

Rev. C | Page 21 of 28

Figure 18 shows power consumption vs. throughput rate for a

3.4 MHz SCLK frequency. In this case, the conversion time is

the same for all cases because the SCLK frequency is a fixed

parameter. Low throughput rates lead to lower current con-

sumptions, with a higher percentage of the time in power-down

mode. Figure 27 shows two AD7466s running with the same

SCLK frequency, but at different throughput rates. The A

throughput rate is higher than the B throughput rate. The

slower the throughput rate, the longer the period of time the

part is in power-down mode, and the average power consump-

tion drops accordingly.

Figure 28 shows the power vs. throughput rate for different

supply voltages and SCLK frequencies. For this plot, all the

elements regarding power consumption that were explained

previously (the influence of the SCLK frequency, the influence

of the throughput rate, and the influence of the supply voltage)

are taken into consideration.

1.4

0.2

0.4

0.6

0.8

1.0

1.2

100

150

200

250

THROUGHPUT (kSPS)

TEMP = 25

°C

VDD = 3.0V, SCLK = 2.4MHz

VDD = 3.0V, SCLK = 3.4MHz

VDD = 1.8V, SCLK = 2.4MHz

VDD = 1.8V, SCLK = 3.4MHz

Figure 28. Power vs. Throughput Rate

for Different SCLK and Supply Voltages

The following examples show calculations for the information

in this section.

Power Consumption Example 1

This example shows that, for a fixed throughput rate, as the

SCLK frequency increases, the average power consumption

drops. From Figure 26, for SCLK A = 3.4 MHz, SCLK B =

1.2 MHz, and a throughput rate of 50 kSPS, which gives a cycle

time of 20 μs, the following values can be obtained:

Conversion Time A = 16 × (1/SCLK A) = 4.7 μs

(23.5% of the cycle time)

Power-Down Time A = (1/Throughput) − Conversion

Time A = 20 μs − 4.7 μs = 15.3 μs (76.5% of the cycle time)

Conversion Time B = 16 × (1/SCLK B) = 13 μs

(65% of the cycle time)

Power-Down Time B = (1/Throughput) − Conversion

Time B = 20 μs − 13 μs = 7 μs (35% of the cycle time)

The average power consumption includes the power dissipated

when the part is converting and the power dissipated when the

part is in power-down mode. The average power dissipated

during conversion is calculated as the percentage of the cycle

time spent when converting, multiplied by the maximum

current during conversion. The average power dissipated in

power-down mode is calculated as the percentage of cycle time

spent in power-down mode, multiplied by the current figure for

power-down mode. In order to obtain the value for the average

power, these terms must be multiplied by the voltage.

Considering the maximum current for each SCLK frequency

for VDD = 1.8 V,

Power Consumption A = ((4.7/20) × 186 μA + (15.3/20) ×

100 nA) × 1.8 V = (43.71 + 0.076) μA × 1.8 V = 78.8 μW

= 0.07 mW

Power Consumption B = ((13/20) × 108 μA + (7/20) ×

100 nA) × 1.8 V = (70.2 + 0.035) μA × 1.8 V = 126.42 μW

= 0.126 mW

It can be concluded that for a fixed throughput rate, the average

power consumption drops as the SCLK frequency increases.

Power Consumption Example 2

This example shows that, for a fixed SCLK frequency, as the

throughput rate decreases, the average power consumption

drops. From Figure 27, for SCLK = 3.4 MHz, Throughput A =

100 kSPS (which gives a cycle time of 10 μs), and Throughput B

= 50 kSPS (which gives a cycle time of 20 μs), the following

values can be obtained:

Conversion Time A = 16 × (1/SCLK) = 4.7 μs

(47% of the cycle time for a throughput of 100 kSPS)

Power-Down Time A = (1/Throughput A) − Conversion

Time A = 10 μs − 4.7 μs = 5.3 μs (53% of the cycle time)

Conversion Time B = 16 × (1/SCLK) = 4.7 μs

(23.5% of the cycle time for a throughput of 50 kSPS)

Power-Down Time B = (1/Throughput B) − Conversion

Time B = 20 μs − 4.7 μs = 15.3 μs (76.5% of the cycle time)

The average power consumption is calculated as explained in

Power Consumption Example 1, considering the maximum

current for a 3.4 MHz SCLK frequency for VDD = 1.8 V.

Power Consumption A = ((4.7/10) × 186 μA + (5.3/10) ×

100 nA) × 1.8 V= (87.42 + 0.053) μA × 1.8 V = 157.4 μW =

0.157 mW

Power Consumption B = ((4.7/20) × 186 μA + (15.3/20) ×

100 nA) × 1.8 V = (43.7 + 0.076) μA × 1.8 V = 78.79 μW =

0.078 mW

It can be concluded that for a fixed SCLK frequency, the average

power consumption drops as the throughput rate decreases.

AD7466BRT-R 数据表(PDF) 21 Page - Analog Devices

AD7466BRT-R 数据表(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载