R5F3650ECNFB datasheet(8/112 Pages) RENESAS

8 / 112 page

R01DS0015EJ0100 Rev.1.00

Page 8 of 109

Feb 07, 2011

M16C/65C Group

1. Overview

1.4

Block Diagram

Figure 1.3 to Figure 1.4 show block diagrams.

Figure 1.3

Block Diagram for the 128-Pin Package

DMAC

(4 channels)

Internal peripheral functions

UART or

clock synchronous serial I/O

(6 channels)

System clock generator

XIN-XOUT

XCIN-XCOUT

PLL frequency synthesizer

On-chip oscillator (125 kHz)

High-speed on-chip oscillator

Clock synchronous serial I/O

(8 bit x 2 channels)

Notes:

1. ROM size depends on MCU type.

2. RAM size depends on MCU type.

Port P5

Port P4

Port P3

Port P2

Port P1

Port P0

VCC2 ports

M16C/60 Series CPU core

R1H

R1L

R0H

R0L

Multiplier

ROM (1)

Memory

RAM (2)

ISP

USP

INTB

FLG

CRC arithmetic circuit

(CRC-CCITT or CRC-16)

Three-phase

motor control circuit

Timer (16 bit)

Outputs (timer A): 5

Inputs (timer B): 6

VCC1 ports

Real-time clock

PWM function (8 bit x 2)

Remote control signal

receiver (2 circuits)

Watchdog timer

(15 bit)

A/D converter

(10-bit resolution x 26

channels)

D/A converter

(8-bit resolution x 2

circuits)

Multi-master I2C-bus interface

(1 channel)

CEC function

Port P13

Port P12

Port P7

Port P8

Port P9

Port P6

Port P14

Port P11

Port P10

On-chip debugger

Voltage detector

Power-on reset

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