Page 9

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

SX8124

24 hours timer synchronized on 50/60Hz mains

ACS - Revision 2.4

October 2010

© Semtech Corp.

5

System architecture

The system is based on its internal timer to track frequency and to disciminate 50 Hz vs 60 Hz supply. If there

is no input on PHASE pin, the system timing will use the internal oscillator (10% precise).

Once the system is locked on the mains phase, its time precision is given by the mains frequency precision.

The period of the output signal on OUT and NOUT is 24 hours. The duty cycle on these pins is equal to the

relative voltage on pin DURATION version the voltage on pin VDD. If DURATION is 1/3 of VDD, OUT will be

high for 8 hours and down for 16 hours.

Remark that when the OUT state is manually modified using the START pin, this does not influence the

internal counter: the OUT (and NOUT) pins will continue to be switched “on” at the end of the 24 hours cycle

and “off” after the programmed duty cycle. The LED outputs is a signal indicating the internal chip status (see

10. LED output).

Figure 4. SX8124 Architecture

LED

60 Hz

detect

Burst gen

DURATION

PHASE

START

Debounce

VDD

OUT

VSS

NOUT

50 Hz

detect

RC

Oscillator

24H

TIMER

ADC

Reset ‘0’

detect

Output

control

Set

duration

Reset

3s detect