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CY2DP1504 数据表(PDF) 5 Page - Cypress Semiconductor

部件名 CY2DP1504
功能描述  1:4 LVPECL Fanout Buffer with Selectable Clock Input
PDF  14 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY2DP1504 数据表(HTML) 5 Page - Cypress Semiconductor

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CY2DP1504
Document Number: 001-56215 Rev. *F
Page 5 of 14
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
Min
Max
Unit
IDD
Operating supply current
All LVPECL outputs floating (internal IDD)–
61
mA
VIH1
Input high voltage, LVPECL input clocks
IN0 and IN0#, IN1 and IN1#
–VDD + 0.3
V
VIL1
Input low voltage, LVPECL input clocks
IN0 and IN0#, IN1 and IN1#
–0.3
–
V
VIH2
Input high voltage, CLK_EN, IN_SEL
VDD = 3.3 V
2.0
VDD + 0.3
V
VIL2
Input low voltage, CLK_EN, IN_SEL
VDD = 3.3 V
–0.3
0.8
V
VIH3
Input high voltage, CLK_EN, IN_SEL
VDD = 2.5 V
1.7
VDD + 0.3
V
VIL3
Input low voltage, CLK_EN, IN_SEL
VDD = 2.5 V
–0.3
0.7
V
VID
[3]
Input differential amplitude
See Figure 2 on page 7
0.4
1.0
V
VICM
Input common mode voltage
See Figure 2 on page 7
0.5
VDD – 0.2
V
IIH
Input high current, all inputs
Input = VDD
[4]
–
150
μA
IIL
Input low current, all inputs
Input = VSS
[4]
–150
–
μA
VOH
LVPECL output high voltage
Terminated with 50
Ω to V
DD – 2.0
[5]
VDD – 1.20 VDD – 0.70
V
VOL
LVPECL output low voltage
Terminated with 50
Ω to V
DD – 2.0
[5]
VDD – 2.0 VDD – 1.63
V
RP
Internal pull-up/pull-down resistance,
LVCMOS logic inputs
CLK_EN has pull-up only
IN_SEL has pull-down only
60
140
k
Ω
CIN
Input capacitance
Measured at 10 MHz; per pin
–
3
pF
Notes
3. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV.
4. Positive current flows into the input pin, negative current flows out of the input pin.
5. Refer to Figure 3 on page 7.
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