CY2DP1504

Document Number: 001-56215 Rev. *F

Page 3 of 14

Pinouts

Figure 1. Pin Diagram – 20-Pin TSSOP Package

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

Q0

Q0#

Q1

Q1#

Q2

Q2#

Q3

Q3#

CLK_EN

IN_SEL

IN0

IN0#

IN1

IN1#

NC

NC

Table 1. Pin Definitions

Pin No.

Pin Name

Pin Type

Description

Power

Ground

2

CLK_EN

Input

Synchronous clock enable. Low-voltage complementary metal oxide

semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL).

When CLK_EN = Low, Q(0:3) outputs are held Low and Q(0:3)# outputs

are held High

3

IN_SEL

Input

Input clock select pin. LVCMOS/LVTTL;

When IN_SEL = Low, the IN0/IN0# differential input pair is active

When IN_SEL = High, the IN1/IN1# differential input pair is active

4

IN0

Input

LVPECL input clock. Active when IN_SEL = Low

5

IN0#

Input

LVPECL complementary input clock. Active when IN_SEL = Low

6

IN1

Input

LVPECL input clock. Active when IN_SEL = High

7

IN1#

Input

LVPECL complementary input clock. Active when IN_SEL = High

8,9

NC

No connection

10,13,18

Power

Power supply

11,14,16,19

Q(0:3)#

Output

LVPECL complementary output clocks

12,15,17,20

Q(0:3)

Output

LVPECL output clocks

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