MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33892

3

Transparent Top View of Package

16

17

20

GND

21

14

15

13

11

24

10

1

SO

GND

HS3

HS1

HS1

HS0

HS0

HS2

FSI

CSNS

IN0

2

3

4

5

6

7

8

9

18

12

19

22

23

TERMINAL FUNCTION DESCRIPTION

Terminal

Terminal Name

Formal Name

Definition

1

2

3

24

IN1

IN2

IN3

IN0

Serial Inputs

The IN0–IN3 high-side input terminals are used to directly control HS0–HS3 high-side

output terminals, respectively. An SPI register determines if each input is activated or

if the input logic state is ORed or ANDed with the SPI instruction. These terminals are

to be driven with 5.0 V CMOS levels, and they have an internal active pull-down current

source.

4

FS

Fault Status

(Active Low)

This terminal is an open drain configured output requiring an external pull-up resistor

LOW. Specific device diagnostic faults are reported via the SPI SO terminal.

5

WAKE

Wake

This terminal is an input that controls the device mode and watchdog timeout feature

if enabled. An internal clamp protects this terminal from high damaging voltages when

the output is current limited with an external resistor. This input has an internal passive

pull-down.

6, 13, 15

GND

Ground

These terminals are the ground for the logic and analog circuitry of the device.

7RST

Reset

This terminal is an input used to initialize the device configuration and fault registers,

as well as place the device in a low-current sleep mode. The terminal also starts the

watchdog timer when transitioning from logic [0] to logic [1]. This terminal should not

pull-down.

8

CS

Chip Select

(Active Low)

This terminal is an input terminal connected to a chip select output of a master

microcontroller (MCU). The MCU determines which device is addressed (selected) to

receive data by pulling the CS terminal of the selected device logic LOW, thereby

enabling SPI communication with the device. Other unselected devices on the serial

link having their CS terminals pulled up logic HIGH disregard the SPI communication

data sent. This terminal has an internal active pull-up current source and requires

CMOS logic levels.

9

SCLK

Serial Clock

This terminal is an input terminal connected to the MCU providing the required bit shift

clock for SPI communication. It transitions one time per bit transferred at an operating

CMOS level serial clock signal is idle between command transfers. The signal is used

to shift data into and out-of the device. This terminal has an internal active pull-down.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com