33892 datasheet(13/28 Pages) FREESCALE

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33892

DYNAMIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions 4.5 V

≤ VDD ≤ 5.5V, 6.0V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical

values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SPI INTERFACE CHARACTERISTICS

Maximum Frequency of SPI Operation

fSPI

–

3.0

MHz

Required Low State Duration for RST (Note 29)

tWRST

–

350

Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 30)

tCS

–

300

Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 30)

tENBL

–

5.0

µs

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 30)

tLEAD

–

167

Required High State Duration of SCLK (Required Setup Time) (Note 30)

tWSCLKh

–

167

Required Low State Duration of SCLK (Required Setup Time) (Note 30)

tWSCLKl

–

167

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 30)

tLAG

–

167

SI to Falling Edge of SCLK (Required Setup Time) (Note 31)

tSI(SU)

–

Falling Edge of SCLK to SI (Required Setup Time) (Note 31)

tSI(HOLD)

–

SO Rise Time

CL = 200 pF

tRSO

–

SO Fall Time

CL = 200 pF

tFSO

–

SI, CS, SCLK, Incoming Signal Rise Time (Note 31)

tRSI

–

SI, CS, SCLK, Incoming Signal Fall Time (Note 31)

tFSI

–

Time from Falling Edge of CS to SO Low Impedance (Note 32)

tSO(EN)

–

145

Time from Rising Edge of CS to SO High Impedance (Note 33)

tSO(DIS)

–

145

Time from Rising Edge of SCLK to SO Data Valid (Note 34)

0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF

tVALID

–

105

Notes

29.

RST

low duration measured with outputs enabled and going to OFF or disabled condition.

30.

Maximum setup time required for the 33892 is the minimum guaranteed time needed from the microcontroller.

31.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

32.

Time required for output status data to be available for use at SO. 1.0 k

Ω on pull-up on CS.

33.

Time required for output status data to be terminated at SO. 1.0 k

Ω on pull-up on CS.

34.

Time required to obtain valid data out from SO following the rise of SCLK.

Freescale Semiconductor, Inc.

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