34LC02 datasheet(7/36 Pages) MICROCHIP

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 2011 Microchip Technology Inc.

DS22029F-page 7

34AA02/34LC02

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

3.6

Device Addressing

A control byte is the first byte received following the

Start condition from the master device. The first part of

the control byte consists of a 4-bit control code which is

set to ‘1010’ for normal read and write operations and

‘0110’ for writing to the write-protect register. The

control byte is followed by three Chip Select bits (A2,

A1, A0). The Chip Select bits allow the use of up to

eight 34XX02 devices on the same bus and are used to

determine which device is accessed. The Chip Select

bits in the control byte must correspond to the logic lev-

els on the corresponding A2, A1 and A0 pins for the

device to respond.

For the SOT-23 package, the A2 pin is not connected.

During device addressing, the A2 Chip Select bit

(Figure 3-2) should be set to ‘0’. Only four 34XX02

SOT-23 packages can be connected to the same bus.

The eighth bit of slave address determines if the master

device wants to read or write to the 34XX02

(Figure 3-2). When set to a one, a read operation is

selected. When set to a zero, a write operation is

selected.

FIGURE 3-2:

CONTROL BYTE

ALLOCATION

4.0

WRITE OPERATIONS

4.1

Byte Write

Following the Start signal from the master, the device

code(4 bits), the Chip Select bits (3 bits) and the R/W

bit, which is a logic low, are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow,

once it has generated an Acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the master is the word address and will be written

into the Address Pointer of the 34XX02.

After receiving another Acknowledge signal from the

34XX02, the master device will transmit the data word

to be written into the addressed memory location. The

34XX02 acknowledges again and the master generates

a Stop condition. This initiates the internal write cycle,

which means that during this time, the 34XX02 will not

generate Acknowledge signals (Figure 4-1). If an

attempt is made to write to the array when the software

or hardware write protection has been enabled, the

device will acknowledge the command, but no data will

be written. The write cycle time must be observed even

if the write protection is enabled.

SCL

SDA

(A)

(B)

(D)

(A)

(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

Operation

Control

Code

Chip

Select

R/W

Read

1010

A2 A1 A0

Write

1010

A2 A1 A0

Write-Protect Register

0110

A2 A1 A0

Start

Read/Write

Slave Address

R/W A

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